公开(公告)号：US20250125298A1

公开(公告)日：2025-04-17

申请号：US18486172

申请日：2023-10-13

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Tzyy-Jang Tseng

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: A chip package structure includes a first chip, a second chip, a plurality of first hybrid bonding pads, a first insulating layer, a first patterned conductive layer, a second patterned conductive layer, and a plurality of first conductive via structures and second conductive via The first chip is electrically connected to the second chip through a plurality of first 5 structures. through silicon vias. The first chip is bonded onto the second chip through the first hybrid bonding pads. The first insulating layer covers the first and the second chips. The first and the second patterned conductive layers are respectively disposed on a first upper surface and a first lower surface of the first insulating layer. The first conductive via structures are electrically connected to the first and the second patterned conductive layers. The second conductive via structures are electrically connected to the first chip and the first patterned conductive layer.

公开(公告)号：US20230163074A1

公开(公告)日：2023-05-25

申请号：US17569509

申请日：2022-01-06

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  John Hon-Shing Lau ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/532 ,  H01L23/495 ,  H01L23/538

CPC classification number: H01L23/5329 ,  H01L23/53238 ,  H01L23/49503 ,  H01L23/5389

Abstract: A chip packaging structure and a manufacturing method thereof are provided. The chip packaging structure includes a substrate, at least one first chip, an adhesive material, a redistribution circuit structure, and multiple second chips. The substrate has a first surface, a second surface opposite to the first surface, and at least one cavity. The at least one first chip is disposed in the at least one cavity. The adhesive material is disposed in the at least one cavity and located between the substrate and the at least one first chip. The redistribution circuit structure is disposed on the first surface of the substrate, and is electrically connected to the at least one first chip. The second chips are disposed on the redistribution circuit structure, and are electrically connected to the redistribution circuit structure.

公开(公告)号：US20220344248A1

公开(公告)日：2022-10-27

申请号：US17235944

申请日：2021-04-21

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chi-Hai Kuo ,  Chia-Yu Peng ,  Tzyy-Jang Tseng

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls, and a molding compound. The redistribution layer includes redistribution circuits, photoimageable dielectric layers, conductive through holes, and chip pads. One of the photoimageable dielectric layers located on opposite two outermost sides has an upper surface and openings. The chip pads are located on the upper surface and are electrically connected to the redistribution circuits through the conductive through holes. The openings expose portions of the redistribution circuits to define solder ball pads. Line widths and line spacings of the redistribution circuits decrease in a direction from the solder ball pads towards the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are disposed on the solder ball pads, and the molding compound at least covers the chip assembly.

公开(公告)号：US11410933B2

公开(公告)日：2022-08-09

申请号：US17314055

申请日：2021-05-07

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Tzyy-Jang Tseng ,  Ra-Min Tain ,  Kai-Ming Yang

IPC: H01L21/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A package structure, including a bridge, an interposer, a first redistribution structure layer, a second redistribution structure layer, and multiple chips, is provided. The bridge includes a silicon substrate, a redistribution layer, and multiple bridge pads. The interposer includes an intermediate layer, multiple conductive vias, multiple first pads, and multiple second pads. The bridge is embedded in the intermediate layer. The bridge pads are aligned with the upper surface. The first redistribution structure layer is disposed on the upper surface of the interposer and is electrically connected to the first pads and the bridge pads. The second redistribution structure layer is disposed on the lower surface of the interposer and is electrically connected to the second pads. The chips are disposed on the first redistribution structure layer and are electrically connected to the first redistribution structure layer. The chips are electrically connected to each other through the bridge.

公开(公告)号：US20220130781A1

公开(公告)日：2022-04-28

申请号：US17567883

申请日：2022-01-04

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  John Hon-Shing Lau

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L21/48

Abstract: A circuit substrate structure includes a circuit substrate, at least two chips, and a bridge element. The circuit substrate has a first surface and a second surface opposite to each other. The chips are arranged in parallel on the first surface of the circuit substrate and electrically connected to the circuit substrate. The chips have active surfaces, back surfaces opposite to the active surfaces, and side surfaces connecting the active surfaces and the back surfaces. The chips include side circuits. The side circuits are arranged on the side surfaces and have first ends and second ends, the first ends extend to the active surfaces along the side surfaces, and the second ends extend to the back surfaces along the side surfaces. The bridge element is arranged on the back surfaces of the chips and electrically connected to the active surfaces of the chips through the side circuits.

公开(公告)号：US20220071000A1

公开(公告)日：2022-03-03

申请号：US17149664

申请日：2021-01-14

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Shao-Chien Lee ,  John Hon-Shing Lau ,  Chen-Hua Cheng ,  Ra-Min Tain

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/40 ,  H05K3/02 ,  H05K3/00

Abstract: The disclosure provides a circuit board structure including at least two sub-circuit boards and at least one connector. Each of the sub-circuit boards includes a plurality of carrier units. The connector is connected between the sub-circuit boards, and a plurality of stress-relaxation gaps are defined between the sub-circuit boards.

公开(公告)号：US20250149503A1

公开(公告)日：2025-05-08

申请号：US18590958

申请日：2024-02-29

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Tzyy-Jang Tseng

IPC: H01L25/065 ,  G02B6/42 ,  H01L23/00 ,  H01L23/498

Abstract: A package structure includes a package substrate, a system on a chip (SoC), at least one input/output circuit, multiple optoelectronic assemblies and an organic interposer. The SoC is disposed on the package substrate and includes a central processing unit (CPU), a graphics processing unit (GPU) and a memory. The input/output circuit is disposed on the package substrate. The optoelectronic assemblies are separately disposed on the package substrate and surround the SoC and the input/output circuit. The organic interposer is disposed on the package substrate. The SoC, the input/output circuit and the optoelectronic assemblies are electrically connected to the package substrate through the organic interposers.

公开(公告)号：US20240014145A1

公开(公告)日：2024-01-11

申请号：US18470427

申请日：2023-09-20

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  John Hon-Shing Lau

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L24/13 ,  H01L21/561 ,  H01L21/78 ,  H01L2924/182 ,  H01L2224/13024

Abstract: An integrated circuit (IC) package structure includes a chip, a redistribution layer (RDL) structure, a molding compound structure and an electromagnetic interference (EMI) shielding structure. The RDL structure is formed on the chip and electrically connected thereto. The molding compound layer is provided on outer surfaces of the chip and the RDL structure. The EMI shielding structure is provided on outer surfaces of the molding compound structure. The molding compound structure layer provided on outer surfaces of the chip and the RDL structure provide protection and reinforcement to multiple faces of the IC package structure; and the EMI shielding structure provided on outer surfaces of the molding compound structure provides EMI protection to multiple faces of the chip and the RDL structure.

公开(公告)号：US20230402441A1

公开(公告)日：2023-12-14

申请号：US18331943

申请日：2023-06-09

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Tzyy-Jang Tseng

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/36 ,  H01L23/38 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  G02B6/42

CPC classification number: H01L25/167 ,  H01L23/5383 ,  H01L23/36 ,  H01L23/5386 ,  H01L23/38 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/50 ,  G02B6/4271 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A package structure includes a circuit board, a package substrate, an electronic/photonic assembly, a film redistribution layer, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on the circuit board and electrically connected to the circuit board. The electronic/photonic assembly includes an ASIC assembly, an EIC assembly, and a PIC assembly. The EIC assembly and the PIC assembly are stacked and disposed on the package substrate and electrically connected to the package substrate via the film redistribution layer. An orthographic projection of the EIC assembly on the film redistribution layer is overlapped with an orthographic projection of the PIC assembly on the film redistribution layer. The heat dissipation assembly is disposed on the electronic/photonic assembly. The optical fiber assembly is disposed on the package substrate and optically connected to the PIC assembly.

公开(公告)号：US11808787B2

公开(公告)日：2023-11-07

申请号：US17342550

申请日：2021-06-09

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  John Hon-Shing Lau ,  Kuo Ching Tien ,  Ra-Min Tain

IPC: H05K1/02 ,  H05K1/03 ,  G01R1/06 ,  G01R1/07 ,  G01R1/073 ,  H05K1/11

CPC classification number: G01R1/07342 ,  G01R1/07328 ,  H05K1/112

Abstract: A probe card testing device includes a first sub-circuit board, a second sub-circuit board, a connecting structure layer, a fixing plate, a probe head and a plurality of conductive probes. The first sub-circuit board is electrically connected to the second sub-circuit board by the connecting structure layer. The fixing plate is disposed on the second sub-circuit board and includes an opening and an accommodating groove. The opening penetrates the fixing plate and exposes a plurality of pads on the second sub-circuit board. The accommodating groove is located on a side of the fixing plate relatively far away from the second sub-circuit board and communicates with the opening. The probe head is disposed in the accommodating groove of the fixing plate. The conductive probes are set on the probe head and in the opening of the fixing plate. One end of the conductive probes is in contact with the corresponding pads, respectively.