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    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250147249A1

    公开(公告)日：2025-05-08

    申请号：US18503194

    申请日：2023-11-07

    Applicant: Unimicron Technology Corp.

    Inventor： John Hon-Shing Lau ,  Tzyy-Jang Tseng

    IPC: G02B6/42

    Abstract: A package structure includes a package substrate, an application specific integrated circuit (ASIC), a plurality of optoelectronic assemblies, and a plurality of organic interposers. The ASIC is disposed on the package substrate and electrically connected to the package substrate. The optoelectronic assemblies are separately disposed on the package substrate and surround the ASIC. Each of the plurality of optoelectronic assemblies includes an electronic integrated circuit (EIC), a photonic integrated circuit (PIC), and a plurality of hybrid bonding pads. The EIC is bonded to the PIC through the plurality of hybrid bonding pads. The plurality of organic interposers are separately disposed on the package substrate and surround the ASIC. The optoelectronic assemblies are electrically connected to the package substrate through the plurality of organic interposers.

    Package structure and optical signal transmitter
    2.
    发明授权
    Package structure and optical signal transmitter 有权

    公开(公告)号：US11860428B1

    公开(公告)日：2024-01-02

    申请号：US17835990

    申请日：2022-06-09

    Applicant: Unimicron Technology Corp.

    Inventor： John Hon-Shing Lau ,  Tzyy-Jang Tseng

    IPC: G02B6/42 ,  H01S5/42

    CPC classification number: G02B6/4274 ,  G02B6/4249 ,  G02B6/4271 ,  G02B6/4295 ,  H01S5/423

    Abstract: A package structure includes a circuit board, a package substrate, a fine metal L/S RDL-substrate, an electronic assembly, a photonic assembly, a heat dissipation assembly, and an optical fiber assembly. The package substrate is disposed on and electrically connected to the circuit board. The fine metal L/S RDL-substrate is disposed on and electrically connected to the package substrate. The electronic assembly includes an application specific integrated circuit (ASIC) assembly, an electronic integrated circuit (EIC) assembly, and a photonic integrated circuit (PIC) assembly which are respectively disposed on the fine metal L/S RDL-substrate and electrically connected to the package substrate by the fine metal L/S RDL-substrate. The heat dissipation assembly is disposed on the electronic assembly. The optical fiber assembly is disposed on the package substrate and electrically connected to the package substrate and the PIC assembly. A packaging method of the VCSEL array chip is presented.

    CIRCUIT CARRIER AND MANUFACTURING METHOD THEREOF AND PACKAGE STRUCTURE
    3.
    发明申请
    CIRCUIT CARRIER AND MANUFACTURING METHOD THEREOF AND PACKAGE STRUCTURE 有权

    公开(公告)号：US20230137841A1

    公开(公告)日：2023-05-04

    申请号：US18089465

    申请日：2022-12-27

    Applicant: Unimicron Technology Corp.

    Inventor： John Hon-Shing Lau ,  Ra-Min Tain ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng ,  Chun-Hsien Chien

    IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K3/00

    Abstract: A circuit carrier includes a substrate, a first build-up circuit structure, a second build-up circuit structure, a fine redistribution structure and at least one conductive through hole. The substrate has a top surface and a bottom surface opposite to each other. The first build-up circuit structure is disposed on the top surface of the substrate and electrically connected to the substrate. The second build-up circuit structure is disposed on the bottom surface of the substrate and electrically connected to the substrate. The fine redistribution structure is directly attached on the first build-up circuit structure, wherein a line width and a line spacing of the fine redistribution structure are smaller than those of the first build-up circuit structure. The conductive through hole penetrates the fine redistribution structure and a portion of the first build-up circuit structure and is electrically connected to the fine redistribution structure and the first build-up circuit structure.

    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220336333A1

    公开(公告)日：2022-10-20

    申请号：US17233551

    申请日：2021-04-19

    Applicant: Unimicron Technology Corp.

    Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Chi-Hai Kuo ,  Tzyy-Jang Tseng

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

    Abstract: A package structure includes at least one first redistribution layer, at least one second redistribution layer, a chip pad, a solder ball pad, a chip, a solder ball, and a molding compound. The first redistribution layer includes a first dielectric layer and a first redistribution circuit that fills a first opening and a second opening of the first dielectric layer. The first dielectric layer is aligned with the first redistribution circuit. The second redistribution layer includes a second and a third dielectric layers and a second redistribution circuit. The third dielectric layer is aligned with the second redistribution circuit. The chip pad and the solder ball pad are electrically connected to the first and the second redistribution circuits respectively. The chip and the solder ball are disposed on the chip pad and the solder ball pad respectively. The molding compound at least covers the chip and the chip pad.

    Circuit board structure and manufacturing method thereof
    8.
    发明授权
    Circuit board structure and manufacturing method thereof 有权

    公开(公告)号：US11516910B1

    公开(公告)日：2022-11-29

    申请号：US17371114

    申请日：2021-07-09

    Applicant: Unimicron Technology Corp.

    Inventor： Chia-Yu Peng ,  John Hon-Shing Lau ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

    IPC: H01R12/52 ,  H05K1/02 ,  H05K1/11 ,  H05K3/24 ,  H05K3/06 ,  H05K3/40

    Abstract: A circuit board structure includes a redistribution structure layer, a build-up circuit structure layer, and a connection structure layer. The redistribution structure layer has a first and second surface, and includes an inner and outer dielectric layer, first connecting pads, and chip pads. A bottom surface of each first connecting pad is aligned with the first surface, and the chip pads are protruded from and located on the second surface. The build-up circuit structure layer includes second connecting pads. The connection structure layer is disposed between the redistribution structure layer and the build-up circuit structure layer and includes a substrate and conductive paste pillars penetrating the substrate. The first connecting pads are electrically connected to the second connecting pads via the conductive paste pillars, respectively. A top surface of each conductive paste pillar is aligned with the first surface of the redistribution structure layer.

    MANUFACTURING METHOD OF THE CHIP PACKAGE STRUCTURE
    9.
    发明申请
    MANUFACTURING METHOD OF THE CHIP PACKAGE STRUCTURE 有权

    公开(公告)号：US20210398925A1

    公开(公告)日：2021-12-23

    申请号：US17463559

    申请日：2021-09-01

    Applicant: Unimicron Technology Corp.

    Inventor： John Hon-Shing Lau ,  Yu-Chi Shen ,  Tzyy-Jang Tseng ,  Chen-Hua Cheng ,  Pei-Wei Wang

    IPC: H01L23/66 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22

    Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

    CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210202407A1

    公开(公告)日：2021-07-01

    申请号：US16729488

    申请日：2019-12-30

    Applicant: Unimicron Technology Corp.

    Inventor： John Hon-Shing Lau ,  Yu-Chi Shen ,  Tzyy-Jang Tseng ,  Chen-Hua Cheng ,  Pei-Wei Wang

    IPC: H01L23/66 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22

    Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

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