公开(公告)号：US11462452B2

公开(公告)日：2022-10-04

申请号：US17156626

申请日：2021-01-24

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L21/78

Abstract: A chip package structure including a chip, a stress buffer layer, a first insulating layer, a redistribution layer, a second insulating layer, and a solder ball is provided. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is disposed on the back surface. A bottom surface of the stress buffer layer is aligned with the back surface of the chip. The redistribution layer is electrically connected to the chip through an opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the redistribution layer. The solder ball is disposed in a blind hole of the second insulating layer and electrically connected to the redistribution layer. A top surface of the solder ball protrudes from an upper surface of the second insulating layer.

公开(公告)号：US20220068872A1

公开(公告)日：2022-03-03

申请号：US17030380

申请日：2020-09-24

Applicant: Unimicron Technology Corp.

Inventor： Chia-Fu Hsu ,  Kai-Ming Yang ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/00

Abstract: A fabrication method of an electronic device bonding structure includes the following steps. A first electronic component including a first conductive bonding portion is provided. A second electronic component including a second conductive bonding portion is provided. A first organic polymer layer is formed on the first conductive bonding portion. A second organic polymer layer is formed on the second conductive bonding portion. Bonding is performed on the first electronic component and the second electronic component through the first conductive bonding portion and the second conductive bonding portion, such that the first electronic component and the second electronic component are electrically connected. The first organic polymer layer and the second organic polymer layer diffuse into the first conductive bonding portion and the second conductive bonding portion after the bonding. An electronic device bonding structure is also provided.

公开(公告)号：US11166387B2

公开(公告)日：2021-11-02

申请号：US16847688

申请日：2020-04-14

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H05K3/22

Abstract: A wiring board including a build-up circuit layer, a patterned conductive layer, first and second adhesion promoting material layers and first and second solder mask layers is provided. The build-up circuit layer has a first surface and a second surface opposite thereto. The patterned conductive layer is disposed on the second surface. The first adhesion promoting material layer is disposed on the first surface and includes at least one first opening. The second adhesion promoting material layer is disposed on the second surface and the patterned conductive layer, and includes at least one second opening. The first solder mask layer is disposed on the first adhesion promoting material layer and includes at least one third opening provided corresponding to the first opening. The second solder mask layer is disposed on the second adhesion promoting material layer and includes at least one fourth opening provided corresponding to the second opening.

公开(公告)号：US20210296291A1

公开(公告)日：2021-09-23

申请号：US16846429

申请日：2020-04-13

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L25/075 ,  H01L33/62 ,  H01L33/52 ,  H01L33/00

Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.

公开(公告)号：US10658282B2

公开(公告)日：2020-05-19

申请号：US16167540

申请日：2018-10-23

Applicant: Unimicron Technology Corp.

Inventor： Cheng-Ta Ko ,  Kai-Ming Yang ,  Yu-Hua Chen ,  Tzyy-Jang Tseng

IPC: H01L23/498

Abstract: A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.

公开(公告)号：US20240251504A1

公开(公告)日：2024-07-25

申请号：US18172324

申请日：2023-02-22

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Chin-Sheng Wang ,  Cheng-Ta Ko ,  Pu-Ju Lin

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H05K3/067 ,  H05K3/4679 ,  H05K2201/09454 ,  H05K2203/0789

Abstract: The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes a line portion, a first insulating layer, and a conductive terminal. The first insulating layer is disposed on the line portion. The conductive terminal is disposed on the first insulating layer and embedded in the first insulating layer to be electrically connected with the line portion. The conductive terminal includes a first portion, a second portion, and a third portion. The first portion protrudes from a surface of the first insulating layer. The second portion is embedded in the first insulating layer and connected to the first portion. The third portion is disposed between the line portion and the second portion. A width of the second portion is greater than a width of the third portion.

公开(公告)号：US20240014145A1

公开(公告)日：2024-01-11

申请号：US18470427

申请日：2023-09-20

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chia-Yu Peng ,  John Hon-Shing Lau

IPC: H01L23/552 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L24/13 ,  H01L21/561 ,  H01L21/78 ,  H01L2924/182 ,  H01L2224/13024

Abstract: An integrated circuit (IC) package structure includes a chip, a redistribution layer (RDL) structure, a molding compound structure and an electromagnetic interference (EMI) shielding structure. The RDL structure is formed on the chip and electrically connected thereto. The molding compound layer is provided on outer surfaces of the chip and the RDL structure. The EMI shielding structure is provided on outer surfaces of the molding compound structure. The molding compound structure layer provided on outer surfaces of the chip and the RDL structure provide protection and reinforcement to multiple faces of the IC package structure; and the EMI shielding structure provided on outer surfaces of the molding compound structure provides EMI protection to multiple faces of the chip and the RDL structure.

公开(公告)号：US11764344B2

公开(公告)日：2023-09-19

申请号：US17209110

申请日：2021-03-22

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang

IPC: H01L33/62 ,  H01L33/06 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L33/54

CPC classification number: H01L33/06 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/5383 ,  H01L23/5386 ,  H01L33/54 ,  H01L2221/6835 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A manufacturing method of a package structure is provided, which includes the following steps. A carrier having a surface is provided. A copper foil layer is laminated on the surface of the carrier. A subtractive process is performed on the copper foil layer to form a copper foil circuit layer on the carrier. The copper foil circuit layer exposes a part of the surface of the carrier. A build-up structure layer is formed on the copper foil circuit layer and the surface of the carrier. A first surface of the copper foil circuit layer is aligned with a second surface of the build-up structure layer. At least one electronic component is disposed on the build-up structure layer. A package colloid is formed to cover the electronic component and the build-up structure layer. The carrier is removed to expose the first surface of the copper foil circuit layer.

公开(公告)号：US20230240023A1

公开(公告)日：2023-07-27

申请号：US17684421

申请日：2022-03-02

Applicant: Unimicron Technology Corp.

Inventor： Wen-Yu Lin ,  Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Chin-Sheng Wang ,  Guang-Hwa Ma ,  Tzyy-Jang Tseng

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K3/467 ,  H05K1/112 ,  H05K2201/0191

Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.

公开(公告)号：US11682658B2

公开(公告)日：2023-06-20

申请号：US17125981

申请日：2020-12-17

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Chia-Hao Chang ,  Tzu-Nien Lee

IPC: H01L25/075 ,  H01L33/54 ,  H01L33/62

CPC classification number: H01L25/0753 ,  H01L33/54 ,  H01L33/62 ,  H01L2933/005 ,  H01L2933/0066

Abstract: A light-emitting package includes an encapsulating member, a plurality of light-emitting components disposed in the encapsulating member, a plurality of first electrode pads, a plurality of second electrode pads, and a plurality of conductive connection structures. The encapsulating member has a first surface and a second surface opposite to each other. Each light-emitting component has a light-emitting surface exposed on the first surface. Both the first electrode pads and the second electrode pads are exposed on the second surface. A first bonding surface of each first electrode pad and a second bonding surface of each second electrode pad are both flush with the second surface. The light-emitting components disposed on the first electrode pads are electrically connected to the first electrode pads. The conductive connection structures passing through the encapsulating member are electrically connected to the light-emitting components and the second electrode pads.