公开(公告)号：US20160233303A1

公开(公告)日：2016-08-11

申请号：US14640033

申请日：2015-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Huai-Tzu Chiang

IPC: H01L29/10 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure with nanowire structures. The semiconductor structure includes a substrate, more than one first source/drain disposed on the substrate, and at least one first nanowire structure disposed on the first source/drain, wherein each first source/drain and the first nanowire structure are on different levels.

Abstract translation: 本发明提供一种具有纳米线结构的半导体结构。 半导体结构包括衬底，设置在衬底上的多于一个的第一源极/漏极，以及设置在第一源极/漏极上的至少一个第一纳米线结构，其中每个第一源极/漏极和第一纳米线结构处于不同的电平。

公开(公告)号：US20160211368A1

公开(公告)日：2016-07-21

申请号：US14636125

申请日：2015-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/42392 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7827

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first dielectric layer and a second dielectric layer thereon; forming a drain layer in the first dielectric layer and the second dielectric layer; forming a gate layer on the second dielectric layer; forming a channel layer in the gate layer; forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer; and forming a source layer in the third dielectric layer and the fourth dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有第一介电层和第二介电层的基板; 在所述第一电介质层和所述第二电介质层中形成漏极层; 在所述第二电介质层上形成栅极层; 在栅极层中形成沟道层; 在栅极层和沟道层上形成第三电介质层和第四电介质层; 以及在所述第三电介质层和所述第四电介质层中形成源极层。

公开(公告)号：US20240047554A1

公开(公告)日：2024-02-08

申请号：US17899604

申请日：2022-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Huai-Tzu Chiang ,  Chuang-Han Hsieh ,  Kai-Lin Lee

IPC: H01L29/66 ,  H01L29/778 ,  H01L23/31

CPC classification number: H01L29/66462 ,  H01L29/778 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/2003

Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A protection layer is formed on the III-V compound barrier layer. An opening is formed penetrating through the protection layer in a vertical direction and exposing a part of the III-V compound barrier layer. A p-type doped III-V compound material is formed in the opening. A patterned barrier layer is formed on the p-type doped III-V compound material. A contact area between the patterned barrier layer and the p-type doped III-V compound material is less than an area of a top surface of the p-type doped III-V compound material.

公开(公告)号：US20240021702A1

公开(公告)日：2024-01-18

申请号：US17885574

申请日：2022-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Chuang-Han Hsieh ,  Huai-Tzu Chiang ,  Kai-Lin Lee

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7786

Abstract: An HEMT includes a first III-V compound layer, a second III-V compound layer, and a III-V compound cap layer. The second III-V compound layer is disposed on the first III-V compound layer. The III-V compound cap layer covers and contacts the second III-V compound layer. The composition of the III-V compound cap layer and the second III-V compound layer are different from each other. A first opening is disposed in the III-V compound cap layer. A first insulating layer includes two first insulating parts and two second insulating parts. The two first insulating parts cover a top surface of the III-V compound cap layer, and the two second insulating parts respectively contact two sidewalls of the first opening. A second opening is disposed between the two first insulating parts and between the two second insulating parts. A gate electrode is disposed in the second opening.

公开(公告)号：US10714607B1

公开(公告)日：2020-07-14

申请号：US16294893

申请日：2019-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Kuan-Hung Liu

IPC: H01L31/0256 ,  H01L29/778 ,  H01L29/207

Abstract: According to an embodiment of the present invention, a high electron mobility transistor (HEMT) includes: a buffer layer on a substrate; a carrier transit layer on the buffer layer; a carrier supply layer on the carrier transit layer; a gate electrode on the carrier supply layer; and a source and a drain adjacent to two sides of the gate electrode. Preferably, the carrier supply layer comprises a concentration gradient of aluminum (Al).

公开(公告)号：US10177231B2

公开(公告)日：2019-01-08

申请号：US15797011

申请日：2017-10-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L29/165 ,  H01L21/3065

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20180102411A1

公开(公告)日：2018-04-12

申请号：US15834082

申请日：2017-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/3247 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/786 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

公开(公告)号：US09837493B2

公开(公告)日：2017-12-05

申请号：US14940867

申请日：2015-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20170117414A1

公开(公告)日：2017-04-27

申请号：US14941674

申请日：2015-11-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Kun-Hsin Chen ,  Tien-I Wu ,  Yu-Ru Yang ,  Huai-Tzu Chiang

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/06 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/167 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: A semiconductor structure including a semiconductor substrate and at least a fin structure formed thereon. The semiconductor substrate includes a first semiconductor material. The fin structure includes a first epitaxial layer and a second epitaxial layer formed between the first epitaxial layer and the semiconductor substrate. The first epitaxial layer includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The second epitaxial layer includes the first semiconductor material and the second semiconductor material. The second epitaxial layer further includes conductive dopants.

公开(公告)号：US20160336401A1

公开(公告)日：2016-11-17

申请号：US15221617

申请日：2016-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L21/324 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3247 ,  H01L29/0669 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides some methods for forming at least two different nanowire structures with different diameters on one substrate. Since the diameter of the nanowire structure will influence the threshold voltage (Vt) and the drive currents of a nanowire field effect transistor, in this invention, at least two nanowire structures with different diameters can be formed on one substrate. Therefore, in the following steps, these nanowire structures can be applied in different nanowire field effect transistors with different Vt and drive currents. This way, the flexibility of the nanowire field effect transistors can be improved.

Abstract translation: 本发明提供了在一个基底上形成具有不同直径的至少两种不同纳米线结构的一些方法。 由于纳米线结构的直径将影响纳米线场效应晶体管的阈值电压（Vt）和驱动电流，所以在本发明中，可以在一个衬底上形成具有不同直径的至少两个纳米线结构。 因此，在以下步骤中，这些纳米线结构可以应用于具有不同Vt和驱动电流的不同纳米线场效应晶体管中。 这样，可以提高纳米线场效应晶体管的灵活性。