公开(公告)号：US20180292449A1

公开(公告)日：2018-10-11

申请号：US15480388

申请日：2017-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuei-Sheng Wu ,  Wen-Jung Liao ,  Wen-Shan Hsiao

IPC: G01R31/26

CPC classification number: G01R31/2601 ,  G01R31/2621

Abstract: A testkey structure including the following components is provided. A fin structure is disposed on a substrate and stretches along a first direction. A first gate structure and a second gate structure are disposed on the fin structure and stretch along a second direction. A first common source region is disposed in the fin structure between the first gate structure and the second gate structure. A first drain region is disposed in the fin structure at a side of the first gate structure opposite to the first common source region. A second drain region disposed in the fin structure at a side of the second gate structure opposite to the first common source region. A testkey structure is symmetrical along a horizontal line crossing the first common source region. The present invention further provides a method of measuring device defect or connection defect by using the same.

公开(公告)号：US12266696B2

公开(公告)日：2025-04-01

申请号：US18608890

申请日：2024-03-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Wen-Jung Liao

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/778

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the I-V compound barrier layer are substantially coplanar.

公开(公告)号：US12206000B2

公开(公告)日：2025-01-21

申请号：US18416764

申请日：2024-01-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Ruey-Chyr Lee

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: A method for forming a high electron mobility transistor is disclosed. A mesa structure having a channel layer and a barrier layer is formed on a substrate. The mesa structure has two first edges extending along a first direction and two second edges extending along a second direction. A passivation layer is formed on the substrate and the mesa structure. A first opening and a plurality of second openings connected to a bottom surface of the first opening are formed and through the passivation layer, the barrier layer and a portion of the channel layer. In a top view, the first opening exposes the two first edges of the mesa structure without exposing the two second edges of the mesa structure. A metal layer is formed in the first opening and the second openings thereby forming a contact structure.

公开(公告)号：US20250015142A1

公开(公告)日：2025-01-09

申请号：US18892494

申请日：2024-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Wen-Jung Liao

IPC: H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, a p-type doped III-V compound layer, an insulation layer, and a gate electrode. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar. The insulation layer is disposed on the III-V compound barrier layer. The insulation layer includes an opening located corresponding to the gate trench in a vertical direction. A part of the p-type doped III-V compound layer is disposed on the insulation layer in the vertical direction. The gate electrode is disposed on the p-type doped III-V compound layer.

公开(公告)号：US20240322008A1

公开(公告)日：2024-09-26

申请号：US18731392

申请日：2024-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou ,  Chih-Tung Yeh

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/3081 ,  H01L29/7787 ,  H01L29/2003 ,  H01L29/205

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer, forming a second barrier layer on the first barrier layer, forming a first hard mask on the second barrier layer, removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

公开(公告)号：US20240136423A1

公开(公告)日：2024-04-25

申请号：US18395657

申请日：2023-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/7786

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

公开(公告)号：US20240071758A1

公开(公告)日：2024-02-29

申请号：US17951119

申请日：2022-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  You-Jia Chang ,  Bo-Yu Chen ,  Yun-Chun Wang ,  Ruey-Chyr Lee ,  Wen-Jung Liao

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L21/0254 ,  H01L21/30612 ,  H01L29/2003 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode layer on the p-type semiconductor layer, and patterning the gate electrode layer to form a gate electrode. Preferably, the gate electrode includes an inclined sidewall.

公开(公告)号：US11742418B2

公开(公告)日：2023-08-29

申请号：US17509053

申请日：2021-10-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Wen-Jung Liao

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L21/76 ,  H01L21/8258 ,  H01L21/8252 ,  H01L29/06

CPC classification number: H01L29/7786 ,  H01L21/76 ,  H01L21/8252 ,  H01L21/8258 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/66 ,  H01L29/66462 ,  H01L2924/13064 ,  H01L2924/14

Abstract: A semiconductor device includes an enhancement mode high electron mobility transistor (HEMT) with an active region and an isolation region. The HEMT includes a substrate, a group III-V body layer, a group III-V barrier layer, a group III-V gate structure and a group III-V patterned structure. The group III-V body layer and the group III-V barrier layer are disposed on the substrate. The group III-V gate structure is disposed on the group III-V barrier layer within the active region. The group III-V patterned structure is disposed on the group III-V barrier layer within the isolation region. The composition of the group III-V patterned structure is the same as the composition of the group III-V gate structure.

公开(公告)号：US20220393005A1

公开(公告)日：2022-12-08

申请号：US17381989

申请日：2021-07-21

Applicant: United Microelectronics Corp.

Inventor： Chih Tung Yeh ,  Wen-Jung Liao

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L21/02 ,  H01L29/66

Abstract: Provided are a nitride semiconductor device and a manufacturing method thereof. The nitride semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first metal layer, a second metal layer and a dielectric layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first metal layer is disposed in the second nitride semiconductor layer. The second metal layer is disposed on the second nitride semiconductor layer. The dielectric layer is disposed between the first metal layer and the second nitride semiconductor layer and/or between the second metal layer and the second nitride semiconductor layer.

公开(公告)号：US11074376B2

公开(公告)日：2021-07-27

申请号：US15497489

申请日：2017-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ching Cheng ,  Chun-Liang Hou ,  Chien-Hung Chen ,  Wen-Jung Liao ,  Min-Chin Hsieh ,  Da-Ching Liao ,  Li-Chin Wang

IPC: G06F30/20

Abstract: A method for analyzing a process output and a method for creating an equipment parameter model are provided. The method for analyzing the process output includes the following steps: A plurality of process steps are obtained. A processor obtains a step model set including a plurality of first step regression models, each of which represents a relationship between N of the process steps and a process output. The processor calculates a correlation of each of the first step regression models. The processor picks up at least two of the first step regression models to be a plurality of second step regression models whose correlations are ranked at top among the correlations of the first step regression models. The processor updates the step model set by a plurality of third step regression models, each of which represents a relationship between M of the process steps and the process output.