公开(公告)号：US20040161888A1

公开(公告)日：2004-08-19

申请号：US10604606

申请日：2003-08-04

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Darrell Rinerson ,  Wayne Kinney ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

IPC: H01L021/00 ,  H01L021/8238 ,  H01L021/20

CPC classification number: G11C13/003 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/2418 ,  H01L27/2436 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/165

Abstract: A multi-resistive state material that uses dopants is provided. A multi-resistive state material can be used in a memory cell to store information. However, a multi-resistive state material may not have electrical properties that are appropriate for a memory device. Intentionally doping a multi-resistive state material to modify the electrical properties can, therefore, be desirable.

Abstract translation: 提供了使用掺杂剂的多阻态材料。 可以在存储器单元中使用多电阻状态材料来存储信息。 然而，多阻态材料可能不具有适合于存储器件的电气特性。 因此，有意地掺杂多电阻状态材料以改变电性能是可取的。

公开(公告)号：US20040160806A1

公开(公告)日：2004-08-19

申请号：US10330170

申请日：2002-12-26

Applicant: Unity Semiconductor Corporation

Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

IPC: G11C011/00

CPC classification number: G11C13/0007 ,  G11C5/147 ,  G11C11/15 ,  G11C13/0004 ,  G11C2213/31

Abstract: Providing a reference voltage to a cross point memory array. The invention is a cross point memory array and some peripheral circuitry that, when activated, provides a reference voltage to a cross point array in order to prevent unselected conductive array lines from floating to an undesired voltage. The peripheral circuitry can be activated before, after or during selection of a specific memory plug. If the peripheral circuitry is activated during selection, only the unselected conductive array lines should be brought to the reference voltage. Otherwise, all the conductive array lines can be brought to the reference voltage.

Abstract translation: 向交叉点存储器阵列提供参考电压。 本发明是一种交叉点存储器阵列和一些外围电路，当被激活时，它向交叉点阵列提供参考电压，以便防止未选择的导电阵列线漂浮到不需要的电压。 外围电路可在特定内存插头选择之前，之后或期间激​​活。 如果外围电路在选择期间被激活，则只有未选择的导电阵列线才能被带到参考电压。 否则，所有导电阵列线可以被带到参考电压。

公开(公告)号：US20040160805A1

公开(公告)日：2004-08-19

申请号：US10330150

申请日：2002-12-26

Applicant: Unity Semiconductor Corporation

Inventor： Darrell Rinerson ,  Christopher J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

IPC: G11C011/00

CPC classification number: G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76

Abstract: Providing a multi-output multiplexor. The invention is multi-output multiplexor that, depending on the control signals, allows various modulating circuits to pass no voltage, pass some voltage or pass all the voltage on one of the mulitplexor's ports., A modulating circuit can be fully turned on, partially turned on, or fully turned off. In a preferred embodiment, a gate circuit is in electrical contact with ground such that when the gate circuit is turned on and its associated modulating circuit is not passing voltage, the multiplexor output associated with the modulating circuit goes to ground.

Abstract translation: 提供多输出多路复用器。 本发明是多输出多路复用器，其根据控制信号允许各种调制电路不通过电压，传递一些电压或通过多路复用器端口之一上的所有电压。调制电路可以完全打开，部分地 打开或完全关闭。 在优选实施例中，门电路与接地电接触，使得当门电路接通并且其相关联的调制电路不通过电压时，与调制电路相关联的多路复用器输出接地。

公开(公告)号：US20040159867A1

公开(公告)日：2004-08-19

申请号：US10605757

申请日：2003-10-23

Applicant: UNITY SEMICONDUCTOR CORPORATION

Inventor： Wayne Kinney ,  Steven W. Longcor ,  Darrell Rinerson ,  Steve Kuo-Ren Hsia

IPC: H01L029/94

CPC classification number: G11C13/003 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  H01L27/2418 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/165

Abstract: A multilayered conductive memory device capable of storing information individually or as part of an array of memory devices is provided. Boundary control issues at the interface between layers of the device due to the use of incompatible materials can be avoided by intentionally doping the conductive metal oxide layers that are comprised of substantially similar materials. Methods of manufacture are also provided herein.

Abstract translation: 提供了能够单独存储信息或作为存储器件阵列的一部分的多层导电存储器件。 通过有意地掺杂由基本上相似的材料构成的导电金属氧化物层，可以避免由于使用不相容的材料而在器件层之间的界面处的边界控制问题。 本文还提供了制造方法。