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    High-density NVRAM
    2.
    发明申请
    High-density NVRAM 有权
    高密度NVRAM

    公开(公告)号：US20040160819A1

    公开(公告)日：2004-08-19

    申请号：US10360005

    申请日：2003-02-07

    Applicant: Unity Semiconductor Corporation

    Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Wayne Kinney

    IPC: G11C011/14

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/77

    Abstract: High density NVRAM. The invention is a an array of memory cells capable of storing at least a megabit of information, each memory cell including a memory plug that includes a memory element that switches from a first resistance state to a second resistance state upon application of a first write voltage of a first polarity and reversibly switches from the second resistance state to the first resistance state upon application of a second write voltage of polarity opposite to the first polarity.

    Abstract translation: 高密度NVRAM。 本发明是能够存储至少一百万个信息的存储器单元的阵列，每个存储单元包括一个存储器插头，该存储器插件包括一个存储元件，该存储器元件在施加第一写入电压时从第一电阻状态切换到第二电阻状态 第一极性的第二写入电压与第一极性相反的第二写入电压可逆地从第二电阻状态切换到第一电阻状态。

    Cross point memory array with memory plugs exhibiting a characteristic hysteresis
    3.
    发明申请
    Cross point memory array with memory plugs exhibiting a characteristic hysteresis 有权
    具有显示特征滞后的存储插头的交叉点存储器阵列

    公开(公告)号：US20040160807A1

    公开(公告)日：2004-08-19

    申请号：US10330900

    申请日：2002-12-26

    Applicant: Unity Semiconductor Corporation

    Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Steve Kuo-Ren Hsia ,  Wayne Kinney ,  Edmond R. Ward ,  Christophe J. Chevallier

    IPC: G11C011/00

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  G11C2213/77

    Abstract: Providing a cross point memory array with memory plugs exhibiting a characteristic hysteresis. The memory plugs exhibit a hysteresis that, in the low resistive state, the first write threshold voltage is the point above which any voltages applied across the memory plug have substantially no effect on the resistive state and below which a voltage pulse will alter the resistance of the memory plug. Similarly, in the high resistive state, the second write threshold voltage is the point below which any voltages applied across the memory plug have substantially no effect on the resistive state and above which a voltage pulse will alter the resistance of the memory plug. The read voltages applied to the memory plug are typically above the first write threshold voltage and lower than the second write threshold voltage.

    Abstract translation: 提供具有表现出特征滞后的存储插件的交叉点存储器阵列。 存储插头表现出滞后现象，在低电阻状态下，第一写入阈值电压是高于其上施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，并且低于该电压脉冲将改变电阻 内存插头。 类似地，在高电阻状态下，第二写入阈值电压是低于施加在存储器插头上的任何电压对电阻状态基本上没有影响的点，并且高于该电压脉冲将改变存储器插头的电阻。 施加到存储器插头的读取电压通常高于第一写入阈值电压并低于第二写入阈值电压。

    REWRITABLE MEMORY WITH NON-LINEAR MEMORY ELEMENT
    4.
    发明申请
    REWRITABLE MEMORY WITH NON-LINEAR MEMORY ELEMENT 失效
    具有非线性记忆元素的可恢复存储器

    公开(公告)号：US20040170040A1

    公开(公告)日：2004-09-02

    申请号：US10604556

    申请日：2003-07-30

    Applicant: UNITY SEMICONDUCTOR CORPORATION

    Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

    IPC: G11C019/08

    CPC classification number: G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/77

    Abstract: A re-writable memory that uses resistive memory cell elements with non-linear IV characteristics is disclosed. Non-linearity is important in certain memory arrays to prevent unselected cells from being disturbed and to reduce the required current. Non-linearity refers to the ability of the element to block the majority of current up to a certain level, but then, once that level is reached, the element allows the majority of the current over and above that level to flow.

    Abstract translation: 公开了一种使用具有非线性IV特性的电阻性存储单元元件的可重写存储器。 在某些存储器阵列中非线性是重要的，以防止未选择的单元被干扰并减少所需的电流。 非线性是指元件将大多数电流阻塞到一定水平的能力，但是一旦达到该电平，该元件允许超过该电平的大部分电流流动。

    2-Terminal trapped charge memory device with voltage switchable multi-level resistance
    5.
    发明申请
    2-Terminal trapped charge memory device with voltage switchable multi-level resistance 失效
    2端子捕获充电存储器件，具有可切换多电平电阻

    公开(公告)号：US20040160812A1

    公开(公告)日：2004-08-19

    申请号：US10634636

    申请日：2003-08-04

    Applicant: Unity Semiconductor Corporation

    Inventor： Darrell Rinerson ,  Wayne Kinney ,  Steven W. Longcor ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia ,  Christophe J. Chevallier

    IPC: G11C011/00

    CPC classification number: G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/79 ,  H01L27/11502 ,  H01L27/11507 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/165

    Abstract: A 2-terminal trapped charge memory device is disclosed with voltage switchable multi-level resistance. The trapped charge memory device has a trapped charge memory body sandwiched between two electrodes. The trapped charge memory body can be made of a variety of semiconducting or insulating materials of single-crystalline, poly-crystalline or amorphous structure while containing current carrier traps whose respective energy levels and degrees of carrier occupancy, modifiable by the height and width of an applied write voltage pulse, determine the resistance. The mechanism of modification can be through carrier tunneling, free carrier capturing, trap-hopping conduction or Frenkel-Poole conduction. The current carrier traps can be created with dopant varieties or an initialization procedure.

    Abstract translation: 公开了具有可电压切换的多电平电阻的2端子俘获电荷存储器件。 捕获的电荷存储器件具有夹在两个电极之间的俘获电荷存储器体。 捕获的电荷存储器主体可以由单晶，多晶或非晶结构的各种半导体或绝缘材料制成，同时包含其各自的能级和载体占有率的载流子阱，其可由 施加写电压脉冲，确定电阻。 修饰的机制可以通过载体隧穿，自由载体捕获，陷阱跳跃传导或Frenkel-Poole传导。 可以用掺杂剂品种或初始化程序产生当前载体陷阱。

    NON-VOLATILE MEMORY WITH A SINGLE TRANSISTOR AND RESISTIVE MEMORY ELEMENT
    8.
    发明申请
    NON-VOLATILE MEMORY WITH A SINGLE TRANSISTOR AND RESISTIVE MEMORY ELEMENT 有权
    具有单个晶体管和电阻存储元件的非易失性存储器

    公开(公告)号：US20040160817A1

    公开(公告)日：2004-08-19

    申请号：US10249848

    申请日：2003-05-12

    Applicant: UNITY SEMICONDUCTOR CORPORATION

    Inventor： Darrell Rinerson ,  Christophe J. Chevallier ,  Steven W. Longcor ,  Wayne Kinney ,  Edmond R. Ward ,  Steve Kuo-Ren Hsia

    IPC: G11C011/14

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C2213/31 ,  G11C2213/79 ,  H01L27/24

    Abstract: Non-volatile memory cell with a single semiconductor device per memory cell. The present invention generally allows for a plurality of memory cells to be formed on a semiconductor substrate that supports a semiconductor device. A multi-resistive state material layer that changes its resistive state between a low resistive state and a high resistive state upon application of a voltage pulse is formed above the substrate, generally at a very high temperature. While the layers fabricated between the substrate and the multi-resistive state material use materials that can withstand high temperature processing, the layers fabricated above the multi-resistive state material do not need to withstand high temperature processing.

    Abstract translation: 每个存储单元具有单个半导体器件的非易失性存储器单元。 本发明通常允许在支撑半导体器件的半导体衬底上形成多个存储单元。 通常在非常高的温度下，在衬底上方形成在施加电压脉冲时改变其电阻状态在低电阻状态和高电阻状态之间的多电阻状态材料层。 虽然在衬底和多电阻状态材料之间制造的层使用可承受高温处理的材料，但是在多电阻状态材料之上制造的层不需要经受高温处理。

    CROSS POINT MEMORY ARRAY USING DISTINCT VOLTAGES
    9.
    发明申请
    CROSS POINT MEMORY ARRAY USING DISTINCT VOLTAGES 有权
    使用差分电压的交点点存储器阵列

    公开(公告)号：US20040160808A1

    公开(公告)日：2004-08-19

    申请号：US10330964

    申请日：2002-12-26

    Applicant: Unity Semiconductor Corporation

    Inventor： Darrell Rinerson ,  Steven W. Longcor ,  Christophe J. Chevallier ,  Edmond R. Ward ,  Wayne Kinney ,  Steve Kuo-Ren Hsia

    IPC: G11C011/00

    CPC classification number: G11C13/0007 ,  G11C11/5685 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/77

    Abstract: Cross point memory array using distinct voltages. The invention is a cross point memory array that applies a first select voltage on one conductive array line, a second select voltage on a second conductive array line, the two conductive array lines uniquely defining a single memory plug. The magnitude of the select voltages depends upon whether a read operation or a write operation is occurring. Additionally, an unselect voltage is applied to the unselected conductive array lines. The unselect voltage can be applied before, after or during the selection process. The unselect voltage is approximately equal to the average of the first select voltage and the second select voltage.

    Abstract translation: 交叉点存储器阵列使用不同的电压。 本发明是一种交叉点存储器阵列，其在一个导电阵列线上施加第一选择电压，在第二导电阵列线上施加第二选择电压，所述两个导电阵列线唯一地限定单个存储器插头。 选择电压的大小取决于是否发生读取操作或写入操作。 此外，未选择的电压被施加到未选择的导电阵列线。 可以在选择过程之前，之后或期间施加取消选择电压。 取消选择电压近似等于第一选择电压和第二选择电压的平均值。

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