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    Semiconductor package having stepwise depression in substrate
    11.
    发明授权
    Semiconductor package having stepwise depression in substrate 有权
    半导体封装在衬底中具有逐步的凹陷

    公开(公告)号：US07902663B2

    公开(公告)日：2011-03-08

    申请号：US12118052

    申请日：2008-05-09

    Applicant: Wen-Jeng Fan

    Inventor： Wen-Jeng Fan

    IPC: H01L23/12

    CPC classification number: H01L23/13 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching area toward two opposing sides of the substrate. The die-attaching material is filled in the stepwise depression. Therefore, the thickness of the die-attaching material under cross-sectional corner(s) of the chip becomes thicker so that a row of the ball terminals away from the central line of the die-attaching area can have greater mobility without changing the appearance, dimensions, thicknesses of the semiconductor package, nor the placing plane of the ball terminals. Accordingly, the row of ball terminals located adjacent the edges or corners of the semiconductor package can withstand larger stresses without ball cracks nor ball drop. The stepwise depression can accommodate the die-attaching material to control bleeding contaminations.

    Abstract translation: 显示出具有增强的球端子移动性的半导体封装。 芯片通过芯片附着材料附着到基板上，其中基板在被覆表面上具有至少一个阶梯式凹陷，以使基板厚度从模具安装区域的中心线逐渐减小到 基质。 模具附着材料填充在阶梯式凹陷中。 因此，芯片的截面角下的模具安装材料的厚度变厚，使得离开模具安装区域的中心线的一排球端子能够在不改变外观的情况下具有更大的移动性 半导体封装的尺寸，厚度，以及球形端子的放置平面。 因此，位于半导体封装的边缘或角落附近的一排球端子可以承受较大的应力，而不会产生球裂纹或球掉落。 阶梯式凹陷可以容纳模具附着材料以控制出血污染。

    Semiconductor package having plural chips side by side arranged on a leadframe
    15.
    发明授权
    Semiconductor package having plural chips side by side arranged on a leadframe 有权
    具有并排布置在引线框上的多个芯片的半导体封装

    公开(公告)号：US07633143B1

    公开(公告)日：2009-12-15

    申请号：US12234894

    申请日：2008-09-22

    Applicant: Wen-Jeng Fan

    Inventor： Wen-Jeng Fan

    IPC: H01L23/495

    CPC classification number: H01L23/49575 ,  H01L23/49503 ,  H01L23/4951 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A semiconductor package with multiple chips side-by-side disposed on a leadframe is revealed, primarily comprising a plurality of leads of a leadframe, a first chip, a second chip, and an encapsulant to encapsulate the chips where the chip thickness of the second chip is larger than the one of the first chip. The first chip and the second chip are individually disposed on a first die-attaching area and on a second die-attaching area of the leads or a die pad of the leadframe. The second die-attaching area is downset relative to the first die-attaching area in a manner that a bottom surface of the encapsulant is closer to the second die-attaching areas than to the first die-attaching areas. Therefore, when chips with different thicknesses are side-by-side disposed, there is no unbalanced mold flow nor package warpage issue.

    Abstract translation: 揭示了具有并排设置在引线框架上的多个芯片的半导体封装，主要包括引线框架，第一芯片，第二芯片和密封剂的多个引线，以封装芯片，其中第二 芯片大于第一芯片之一。 第一芯片和第二芯片分别设置在引线框架的第一管芯附接区域和引线的第二管芯附着区域或管芯焊盘上。 第二管芯安装区域相对于第一管芯附着区域以与第一管芯附着区域相比更靠近第二管芯附着区域的方式下降。 因此，当并排布置具有不同厚度的芯片时，没有不平衡的模具流动和封装翘曲问题。

    COL (CHIP-ON-LEAD) MULTI-CHIP PACKAGE
    16.
    发明申请
    COL (CHIP-ON-LEAD) MULTI-CHIP PACKAGE 有权
    COL（CHIP-ON-LEAD）多芯片包装

    公开(公告)号：US20090302441A1

    公开(公告)日：2009-12-10

    申请号：US12133892

    申请日：2008-06-05

    Applicant: Wen-Jeng Fan

    Inventor： Wen-Jeng Fan

    IPC: H01L23/495

    CPC classification number: H01L23/49575 ,  H01L23/4951 ,  H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/49112 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

    Abstract: A Chip-On-Lead (COL) multi-chip package is revealed, primarily comprising a plurality of leads, a first chip disposed on the first leads, one or more second chips stacked on the first chip, and an encapsulant. The leads have a plurality of internal leads encapsulated inside the encapsulant where the internal leads are fully formed on a downset plane toward and parallel to a bottom surface of the encapsulant. The height between the internal leads to a top surface of the encapsulant is three times or more greater than the height between the internal leads and the bottom surface. Since the number and the thickness of the second chips is under controlled, tile thickness between the top surface of the encapsulant and the most adjacent one of the second chips is about the same as the one between the internal leads and the bottom surface of the encapsulant. Therefore, the internal leads of the leads without downset bends in the encapsulant can balance the upper and lower mold flows and carry more chips without shifting nor tilting.

    Abstract translation: 揭示了芯片引线（COL）多芯片封装，主要包括多个引线，设置在第一引线上的第一芯片，堆叠在第一芯片上的一个或多个第二芯片和密封剂。 引线具有封装在密封剂内部的多个内部引线，其中内部引线完全形成在朝向并平行于密封剂的底表面的凹陷平面上。 位于密封剂顶表面的内部引线之间的高度是内部引线和底部表面之间的高度的三倍或更大。 由于第二芯片的数量和厚度受到控制，密封剂的顶表面与第二芯片中最相邻的芯片之间的瓦片厚度与密封剂的内部引线和底部表面之间的厚度大致相同 。 因此，密封剂中引线没有下弯曲的内部引线可平衡上下模流，并承载更多的芯片而不会移位或倾斜。

    Substrate package structure
    18.
    发明申请
    Substrate package structure 审中-公开
    基板封装结构

    公开(公告)号：US20090160041A1

    公开(公告)日：2009-06-25

    申请号：US12071611

    申请日：2008-02-25

    Applicant: Wen-Jeng Fan

    Inventor： Wen-Jeng Fan

    IPC: H01L23/498

    CPC classification number: H01L23/5386 ,  H01L21/565 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A substrate package structure is disclosed herein. The substrate package structure includes a packaging substrate provided with a plurality of chip carriers set at one surface of the packaging substrate, wherein those chip carriers are formed by intersecting a plurality of cutting streets; a plurality of through holes set at those cutting streets and set around those chip carriers; and a plurality of molding areas set on another surface of the packaging substrate and opposite to those chip carriers, wherein those molding areas are adjacent to those through holes. Hence, those through holes may be flowed by the molding compound to form a plurality of molding bumps around those chip carriers so as to improve the crack problem of the chip and/or the substrate.

    Abstract translation: 本文公开了一种衬底封装结构。 衬底封装结构包括设置有设置在封装衬底的一个表面处的多个芯片载体的封装衬底，其中这些芯片载体通过与多个切割街道相交而形成; 设置在那些切割街道处的多个通孔并围绕这些芯片载体设置; 以及设置在所述包装基板的另一表面上且与所述芯片载体相对的多个模制区域，其中所述模制区域与所述通孔相邻。 因此，这些通孔可以通过模塑料流动，以在这些芯片载体周围形成多个模制凸块，从而改善芯片和/或基板的裂纹问题。

    Stacked assembly of semiconductor packages with fastening lead-cut ends of leadframe
    19.
    发明申请
    Stacked assembly of semiconductor packages with fastening lead-cut ends of leadframe 有权
    半导体封装的堆叠组件，具有引线框架的紧固引线端

    公开(公告)号：US20090127678A1

    公开(公告)日：2009-05-21

    申请号：US11984771

    申请日：2007-11-21

    Applicant: Wen-Jeng Fan

    Inventor： Wen-Jeng Fan

    IPC: H01L23/495

    CPC classification number: H01L23/49541 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A stacked assembly of semiconductor packages primarily comprises a plurality of stacked semiconductor packages. Each semiconductor package includes an encapsulant, at least a chip, and a plurality of external leads of a leadframe, where the external leads are exposed and extended from a plurality of sides of the encapsulant. Each external lead of an upper semiconductor package has a U-shaped cut end when package singulation. The U-shaped cut ends are configured for locking to the soldered portion of a corresponding external lead of a lower semiconductor package where the U-shaped cut ends and the soldered portions by soldering materials. Therefore, the stacked assembly has a larger soldering area and stronger lead reliability to enhance the soldering points to against the effects of impacts, thermal shocks, and thermal cycles.

    Abstract translation: 半导体封装的堆叠组件主要包括多个堆叠的半导体封装。 每个半导体封装包括密封剂，至少芯片和引线框架的多个外部引线，其中外部引线从密封剂的多个侧面暴露和延伸。 当封装分割时，上半导体封装的每个外部引线具有U形切割端。 U形切割端被构造成用于通过焊接材料锁定到U形切割端的下半导体封装的相应外部引线的焊接部分和焊接部分。 因此，堆叠组件具有更大的焊接面积和更强的导线可靠性，以增强焊接点以抵抗冲击，热冲击和热循环的影响。

    Semiconductor package and substrate for the same
    20.
    发明申请
    Semiconductor package and substrate for the same 审中-公开
    半导体封装和衬底相同

    公开(公告)号：US20090096070A1

    公开(公告)日：2009-04-16

    申请号：US12068623

    申请日：2008-02-08

    Applicant: Wen-Jeng Fan ,  Yi-Ling Liu

    Inventor： Wen-Jeng Fan ,  Yi-Ling Liu

    IPC: H01L23/495 ,  H05K7/18

    CPC classification number: H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

    Abstract: A semiconductor package is revealed with a special designed substrate. The substrate has a plurality of fingers, a dummy metal pattern, and at least a peripheral slot penetrating through the substrate. The dummy metal pattern is aligned to two opposing sides of the peripheral slot and is electrically isolated from the fingers. A chip is disposed on the substrate and is electrically connected to the fingers. An encapsulant is completely filled the peripheral slot. The peripheral slot can enhance the mold flow and eliminate the mold flash. The shape of the dummy metal pattern aligned to the peripheral slot is used to offer stiffening edges to prevent the substrate from warpage and from breakage at peripheries, to enhance the thermal stress resistance due to thermal cycles, and to avoid damages to the chip.

    Abstract translation: 使用特殊设计的基板显露半导体封装。 衬底具有多个指状物，虚拟金属图案，以及穿透衬底的至少一个外围槽。 虚设金属图案与外围槽的两个相对的侧对齐并且与手指电隔离。 芯片设置在基板上并与手指电连接。 密封剂完全填充外围槽。 外围槽可以增强模具流动，消除模具闪光。 与外围槽对准的虚设金属图案的形状用于提供加强边缘，以防止基板翘曲并在周边断裂，从而提高由于热循环引起的热应力阻力，并避免损坏芯片。

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