公开(公告)号：US08592992B2

公开(公告)日：2013-11-26

申请号：US13326128

申请日：2011-12-14

Applicant: Yaojian Lin ,  Kang Chen

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L23/522

CPC classification number: H01L24/06 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring. In another embodiment, an insulating layer is formed over the semiconductor die for structural support, a build-up interconnect structure is formed over the semiconductor die, and a conductive interconnect structure is formed within the first through-mold-hole.

Abstract translation: 半导体器件具有半导体管芯。 在半导体管芯上形成密封剂。 导电微通孔阵列形成在半导体管芯的覆盖区外部的密封剂上。 通过密封剂形成具有阶梯通孔结构的第一贯通孔，以露出导电微通孔阵列。 在一个实施例中，形成导电微通孔阵列还包括在密封剂和半导体管芯上方形成绝缘层，形成穿过半导体管芯外部的绝缘层的微通孔阵列，并在绝缘层上形成导电层 。 在另一个实施例中，形成导电微通孔阵列还包括形成导电环。 在另一个实施例中，在用于结构支撑的半导体管芯上形成绝缘层，在半导体管芯上形成积聚互连结构，并且在第一通孔内形成导电互连结构。

公开(公告)号：US08575018B2

公开(公告)日：2013-11-05

申请号：US12628631

申请日：2009-12-01

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Pandi Chelvam Marimuthu ,  Rajendra D. Pendse

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Pandi Chelvam Marimuthu ,  Rajendra D. Pendse

IPC: H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/29 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05155 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1411 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor wafer has a first conductive layer formed over its active surface. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A UBM layer is formed around a bump formation area over the second conductive layer. The UBM layer can be two stacked metal layers or three stacked metal layers. The second conductive layer is exposed in the bump formation area. A second insulating layer is formed over the UBM layer and second conductive layer. A portion of the second insulating layer is removed over the bump formation area and a portion of the UBM layer. A bump is formed over the second conductive layer in the bump formation area. The bump contacts the UBM layer to seal a contact interface between the bump and second conductive layer.

Abstract translation: 半导体晶片具有在其有效表面上形成的第一导电层。 第一绝缘层形成在衬底和第一导电层上。 在第一导电层和第一绝缘层上形成第二导电层。 在第二导电层上方的凸块形成区域周围形成UBM层。 UBM层可以是两个堆叠的金属层或三个堆叠的金属层。 第二导电层暴露在凸块形成区域中。 在UBM层和第二导电层上形成第二绝缘层。 第二绝缘层的一部分在凸块形成区域和UBM层的一部分上被去除。 在凸块形成区域中的第二导电层上形成凸块。 凸块接触UBM层以密封凸点和第二导电层之间的接触界面。

公开(公告)号：US20130249105A1

公开(公告)日：2013-09-26

申请号：US13426552

申请日：2012-03-21

Applicant: Yaojian Lin ,  Kang Chen

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/02165 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/014

Abstract: A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.

Abstract translation: 半导体器件具有形成在半导体管芯上的半导体管芯和第一绝缘层。 可以在第一绝缘层中形成多个第一微通孔。 导电层形成在第一微孔中并在第一绝缘层之上。 在第一绝缘层和导电层上形成第二绝缘层。 去除第二绝缘层的一部分以暴露导电层并在导电层上的第二绝缘层中形成多个第二微孔。 第二微孔可以是微通孔，微通孔环或微通孔。 去除第二绝缘层的部分在导电层上留下第二绝缘层的岛。 在导电层上形成凸点。 在凸起上的第二微孔中形成第三绝缘层。 第二个微孔提供应力消除。

公开(公告)号：US08502339B2

公开(公告)日：2013-08-06

申请号：US12813315

申请日：2010-06-10

Applicant: Yaojian Lin ,  Robert C. Frye

Inventor： Yaojian Lin ,  Robert C. Frye

IPC: H01L21/02

CPC classification number: H01L23/52 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/64 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/16 ,  H05K3/20 ,  H05K3/284 ,  H05K3/4644 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.

公开(公告)号：US20130181323A9

公开(公告)日：2013-07-18

申请号：US12726880

申请日：2010-03-18

Applicant: Yaojian Lin

Inventor： Yaojian Lin

IPC: H01L23/52 ,  H01L21/768

CPC classification number: H01L28/10 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5228 ,  H01L23/528 ,  H01L24/73 ,  H01L28/40 ,  H01L2224/48463 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a first insulating layer formed over a first surface of a polymer matrix composite substrate. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. The second conductive layer is wound to exhibit inductive properties. A third conductive layer is formed between the first conductive layer and second conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. A bump is formed over the second conductive layer. A fourth insulating layer can be formed over a second surface of the polymer matrix composite substrate. Alternatively, the fourth insulating layer can be formed over the first insulating layer prior to forming the first conductive layer.

Abstract translation: 半导体器件具有形成在聚合物基质复合衬底的第一表面上的第一绝缘层。 在第一绝缘层上形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 在第二绝缘层和第一导电层上形成第二导电层。 第二导电层被卷绕以表现出感应特性。 在第一导电层和第二导电层之间形成第三导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 在第二导电层上形成凸块。 可以在聚合物基质复合衬底的第二表面上形成第四绝缘层。 或者，可以在形成第一导电层之前，在第一绝缘层上形成第四绝缘层。

公开(公告)号：US08487438B2

公开(公告)日：2013-07-16

申请号：US12484099

申请日：2009-06-12

Applicant: Yaojian Lin ,  Byung Tai Do ,  Romeo Emmanuel P. Alvarez

Inventor： Yaojian Lin ,  Byung Tai Do ,  Romeo Emmanuel P. Alvarez

IPC: H01L23/485

CPC classification number: H01L24/06 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: An integrated circuit solder bumping system provides a substrate and forms a redistribution layer on the substrate. An insulation layer is formed on the redistribution layer. The insulation layer has a plurality of openings therethrough. A first UBM layer of titanium is deposited on the insulation layer and in the openings therethrough. A second UBM layer of chromium/copper alloy is deposited on the first UBM layer. A third UBM layer of copper is deposited on the second UBM layer. UBM pads of at least two different sizes are formed from the UBM layers. Solder paste is printed over at least some of the UBM pads. The solder paste is reflowed to form at least smaller solder bumps on at least some of the UBM pads. Bigger solder bumps are formed on at least some of the UBM pads.

Abstract translation: 集成电路焊料凸块系统提供衬底并在衬底上形成再分布层。 在再分布层上形成绝缘层。 绝缘层具有穿过其中的多个开口。 第一UBM层钛沉积在绝缘层上和通过其中的开口中。 第二UBM层的铬/铜合金沉积在第一UBM层上。 铜的第三UBM层沉积在第二UBM层上。 具有至少两种不同尺寸的UBM焊盘由UBM层形成。 至少一些UBM垫上印有焊膏。 焊膏被回流以在至少一些UBM焊盘上形成至少较小的焊料凸块。 在至少一些UBM垫上形成更大的焊料凸块。

公开(公告)号：US08466557B2

公开(公告)日：2013-06-18

申请号：US12756067

申请日：2010-04-07

Applicant: Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Rajendra D. Pendse

Inventor： Yaojian Lin ,  Pandi Chelvam Marimuthu ,  Rajendra D. Pendse

IPC: H01L23/48

CPC classification number: H05K3/3452 ,  H01L24/03 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H05K3/388 ,  H05K2201/2081 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2224/48

Abstract: A solder bump confinement system is provided includes a substrate; a contact material patterned on the substrate; an inner passivation layer deposited over the contact material and the substrate; an under bump material pad over the contact material; an under bump material defining layer, having a bump opening contained therein, directly on the under bump material pad in which the under bump material defining layer has a thickness in the range of 200 Angstrom to 1500 Angstrom; and a system interconnect formed over the contact material and coupled to the under bump material defining layer and the under bump material pad through the bump opening.

Abstract translation: 提供了一种焊料凸块限制系统，包括：基板; 图案化在基板上的接触材料; 沉积在接触材料和基底上的内部钝化层; 触点材料上的凸块下垫材料垫; 一个凹凸材料限定层，其中包含一个凸起开口，其直接位于下凸块材料垫上，其中下凸块材料限定层的厚度在200埃至1500埃的范围内; 以及形成在所述接触材料上并且通过所述凸起开口耦合到所述下凸块材料限定层和所述下凸块材料垫的系统互连。

公开(公告)号：US08445323B2

公开(公告)日：2013-05-21

申请号：US13423739

申请日：2012-03-19

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure.

Abstract translation: 半导体器件包括IPD结构，安装到具有倒装芯片互连的IPD结构的第一半导体管芯和与第一半导体管芯相邻设置的多个第一导电柱。 半导体器件还包括设置在第一导电柱和第一半导体管芯之上的第一模塑料，与第一半导体管芯上的第一导电柱结合的芯结构以及设置在芯结构中的多个导电TSV。 半导体器件还包括设置在芯结构上的多个第二导电柱，安装在芯结构上的第二半导体管芯，以及设置在第二导电柱和第二半导体管芯上的第二模塑料。 第二半导体管芯与芯结构电连接。

公开(公告)号：US20130113092A9

公开(公告)日：2013-05-09

申请号：US13333739

申请日：2011-12-21

Applicant: Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L23/52 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US08436439B2

公开(公告)日：2013-05-07

申请号：US12871401

申请日：2010-08-30

Applicant: Reza A. Pagaila ,  Rui Huang ,  Yaojian Lin

Inventor： Reza A. Pagaila ,  Rui Huang ,  Yaojian Lin

IPC: H01L27/14 ,  H01L31/00

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.

Abstract translation: 通过在衬底上形成互连结构来制造半导体器件。 将半导体管芯安装到互连结构。 半导体管芯与互连结构电连接。 在互连结构上形成接地焊盘。 在半导体管芯和互连结构上形成密封剂。 在形成密封剂之前，可以在半导体管芯上方形成屏蔽笼。 在形成互连结构之后，在密封剂之上形成屏蔽层，以便相对于器件间干扰来隔离半导体管芯。 屏蔽层符合密封剂的几何形状并且电连接到接地垫。 屏蔽层可以通过导电柱电连接到地面。 在互连结构上形成背面互连结构，与半导体管芯相对。