公开(公告)号：US20190102290A1

公开(公告)日：2019-04-04

申请号：US16190043

申请日：2018-11-13

Applicant: Wolley Inc.

Inventor： Chuen-Shen Bernard Shung

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F12/0804 ,  G06F12/1009 ,  G11C29/04

CPC classification number: G06F12/0238 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0685 ,  G06F11/1068 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/403 ,  G06F2212/608 ,  G06F2212/7211 ,  G11C29/52 ,  G11C2029/0409

Abstract: A method and apparatus of wear leveling control for storage class memory are disclosed. According to the present invention, whether current data to be written to a nonvolatile memory corresponds to a write cache hit is determined. If the current data to be written corresponds to the write cache hit, the current data are written to a write cache as well as to a designated location in the nonvolatile memory different from a destined location in the nonvolatile memory. If the current data to be written corresponds to a write cache miss, the current data are written to the destined location in the nonvolatile memory. If the current data to be written corresponds to the write cache miss and the write cache is not full, the current data is also written to the write cache. In another embodiment, the wear leveling control technique also includes address rotation process to achieve long-term wear leveling as well.

公开(公告)号：US20180321878A1

公开(公告)日：2018-11-08

申请号：US15915147

申请日：2018-03-08

Applicant: SK hynix Inc.

Inventor： Do-Sun HONG ,  Dong-Gun KIM ,  Yong-Ju KIM

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0659 ,  G06F3/0616 ,  G06F3/0644 ,  G06F3/0679 ,  G06F12/10 ,  G06F2212/1036 ,  G06F2212/202 ,  G06F2212/657

Abstract: A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.

公开(公告)号：US20180276114A1

公开(公告)日：2018-09-27

申请号：US15693275

申请日：2017-08-31

Applicant: Toshiba Memory Corporation

Inventor： Sho KODAMA

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F3/0608 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/065 ,  G06F3/0679 ,  G06F12/0638 ,  G06F2212/1036 ,  G06F2212/1044 ,  G06F2212/205 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7206

Abstract: A memory controller controls first and second memory, and includes a control unit. In response to a first write command from a host, which designates a logical address for first data to be written to the first memory, the control unit determines whether mapping of the logical address is presently being managed in a first mode with a first cluster size or a second mode with a second cluster size that is smaller than the first cluster size, changes first mapping data for the logical address stored in a first table in the second memory, from the first cluster size to the second cluster size, if the mapping of the logical address is being managed in the first mode and the first mapping data can be compressed at a ratio lower than a first compression ratio, and writes the first data to a physical address of the first memory.

公开(公告)号：US10073642B2

公开(公告)日：2018-09-11

申请号：US15217510

申请日：2016-07-22

Applicant: SK hynix Inc.

Inventor： Ik Joon Son

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0629 ,  G06F3/0604 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F12/02 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7204 ,  G06F2212/7205 ,  G06F2212/7208

Abstract: A method for operating a data storage device including a plurality of memory regions. The method includes performing a read operation for a first memory region, increasing a read count based on read sequences of the first memory region and a second memory region which has been read before the read operation for the first memory region, and performing a management operation for the plurality of memory regions based on the read count.

公开(公告)号：US20180196622A1

公开(公告)日：2018-07-12

申请号：US15741600

申请日：2015-11-05

Applicant: HITACHI, LTD.

Inventor： Masatsugu OSHIMI ,  Junji OGAWA ,  Yoshihiro OIKAWA

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0652 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/16 ,  G06F2212/1036 ,  G06F2212/7211

Abstract: This nonvolatile memory device has a blockwise-erase nonvolatile memory including a plurality of physical areas, and also has a memory controller which transmits one of a plurality of types of commands to the nonvolatile memory. After an erase command to erase one of the physical areas has been transmitted, but before a response to that erase command is received, the memory controller determines whether to suspend the ongoing erasure of the physical area, on the basis of whether there is a command to be transmitted and/or on the basis of the degree of deterioration of the physical area being erased. If the determination is affirmative, the memory controller transmits a command to the nonvolatile memory to suspend the erasure.

公开(公告)号：US10019166B2

公开(公告)日：2018-07-10

申请号：US15130320

申请日：2016-04-15

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Kanishk Rastogi ,  Sanoj Kizhakkekara Unnikrishnan ,  Anand Mitra

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0608 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0658 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7205 ,  G06F2212/7211

Abstract: Embodiments of the present disclosure provide a memory-efficient mechanism for identifying memory blocks with a low wear count. More particularly, embodiments of the present disclosure provide a mechanism for identifying a memory block whose wear count is within the bottom p % of all wear counts associated with memory blocks in a storage system. If a memory controller always performs the garbage collection operation on a memory block whose wear count is within the bottom p % of all wear counts, then the memory controller is expected to utilize the remaining memory blocks (e.g., memory blocks whose wear count is within the upper (100-p) % of all wear counts) efficiently and level the wear count of at least the remaining memory blocks.

公开(公告)号：US20180188984A1

公开(公告)日：2018-07-05

申请号：US15396547

申请日：2016-12-31

Applicant: Western Digital Technologies, Inc.

Inventor： Ming-Yu Tai ,  Yun-Tzuo Lai ,  Yung-Li Ji ,  Haining Liu

IPC: G06F3/06 ,  G06F11/07 ,  G06F12/02

CPC classification number: G11C16/3495 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/076 ,  G06F12/02 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/1036 ,  G06F2212/1044 ,  G06F2212/7211 ,  G11C16/349

Abstract: A method, system, and apparatus are provided for retiring computer memory blocks. Two overall schemes are provided for separating poorly functioning blocks from normally functioning blocks. In a first scheme, after data relocation is finished, firmware remembers the old physical memory block. As soon as the system writes to the old physical memory block with new data, firmware issues a read again and receives back a count of error bits. If the returned error bits are still high, then the system identifies the block as being weak and retires the block. In a second scheme, firmware tracks statistics for data relocates, block reads, activity timers, among other statistics. If some blocks have abnormal activities (e.g., too many data relocates, too many reads, etc.), then the system may identify the block as being weak and may retire the physical memory block.

公开(公告)号：US20180181328A1

公开(公告)日：2018-06-28

申请号：US15388768

申请日：2016-12-22

Applicant: Western Digital Technologies, Inc.

Inventor： Adam Michael ESPESETH ,  Brent William JACOBS

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02

CPC classification number: G06F3/0622 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/5083 ,  G06F9/52 ,  G06F12/0246 ,  G06F12/0284 ,  G06F12/1009 ,  G06F2212/1036 ,  G06F2212/1044 ,  G06F2212/1048 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7208

Abstract: A method and apparatus for accessing a storage device is disclosed. More specifically, for load balancing by dynamically transferring memory address range assignments. In one embodiment, a storage device receives, from a host apparatus, an access request directed at two or more storage addresses, assigns, based on a first storage address of the two or more storage addresses, the access request to a first processor of two or more processors of the storage device, obtains a local memory lock based on the first storage address, determines, based on a second storage address of the two or more storage addresses, that the second storage address is assigned to a second processor of the two or more processors, obtains a remote memory lock from the second processor based on the second storage address and processes the access request.

公开(公告)号：US20180173621A1

公开(公告)日：2018-06-21

申请号：US15897797

申请日：2018-02-15

Applicant: Micron Technology, Inc.

Inventor： David A. Palmer

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/04 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7203

Abstract: The present disclosure includes methods and systems for coalescing unaligned data. One method includes receiving a first write command associated with a first unaligned portion of data, receiving a second write command associated with a second unaligned portion of data, and coalescing the first unaligned portion of data and the second unaligned portion of data, wherein coalescing includes writing the first unaligned portion of data and the second unaligned portion of data to a page in a memory device.

公开(公告)号：US09971511B2

公开(公告)日：2018-05-15

申请号：US15017391

申请日：2016-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0631 ,  G06F3/0641 ,  G06F3/0644 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/1041 ,  G06F2212/205 ,  G06F2212/217 ,  G06F2212/222 ,  G06F2212/7208

Abstract: A hybrid module includes one or more memory modules, each of which includes one or more memory devices and a memory controller, one or more storage modules, each of which includes one or more storage devices and a storage controller. A host interface of the hybrid module includes a main controller and provides an interface with the memory controller and the storage controller. A transaction-based memory interface provides an interface between the main controller and a host memory controller.