公开(公告)号：US12130884B2

公开(公告)日：2024-10-29

申请号：US17374988

申请日：2021-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Peng Gu ,  Krishna Malladi ,  Hongzhong Zheng ,  Dimin Niu

IPC: G06F17/16 ,  G06F12/0802 ,  G06F12/0877 ,  G06N3/008 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06F17/16 ,  G06F12/0802 ,  G06F12/0877 ,  G06N3/008 ,  G06N3/045 ,  G06N3/063 ,  G06F2212/1024 ,  G06F2212/1036 ,  G06F2212/22 ,  G06N3/08

Abstract: A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory bank, a peripheral lookup table stored in the memory bank, and a first vector buffer to store a first vector that is used as a row address into the lookup table. The circuit includes a second vector buffer to store a second vector that is used as a column address into the lookup table, and lookup table buffers to receive and store lookup table entries from the lookup table. The circuit further includes adders to sum the first product and a second product, and an output buffer to store the sum. The lookup table buffers determine a product of the first vector and the second vector without performing a multiply operation. The embodiments include a hierarchical lookup architecture to reduce latency. Accumulation results are propagated in a systolic manner.

公开(公告)号：US20240152274A1

公开(公告)日：2024-05-09

申请号：US18486826

申请日：2023-10-13

Applicant: Memory Technologies LLC

Inventor： Kimmo J. Mylly ,  Jani J. Klint ,  Jani Hyvonen ,  Tapio Hill ,  Jukka-Pekka Vihmalo ,  Matti Floman

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0888 ,  G11C7/10

CPC classification number: G06F3/0607 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0888 ,  G11C7/1072 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1036 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7206 ,  Y02D10/00

Abstract: A method includes, in one non-limiting embodiment, receiving a command originating from an initiator at a controller associated with a non-volatile mass memory coupled with a host device, the command being a command to write data that is currently resident in a memory of the host device to the non-volatile mass memory; moving the data that is currently resident in the memory of the host device from an original location to a portion of the memory allocated for use at least by the non-volatile mass memory; and acknowledging to the initiator that the command to write the data to the non-volatile mass memory has been executed. An apparatus configured to perform the method is also described.

公开(公告)号：US11875836B2

公开(公告)日：2024-01-16

申请号：US17339854

申请日：2021-06-04

Applicant: Kepler Computing Inc.

Inventor： Christopher B. Wilkerson ,  Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Amrita Mathuriya

IPC: G11C11/00 ,  G11C11/22 ,  G11C13/00 ,  G11C11/16 ,  G11C16/10 ,  G06F12/02 ,  G06F11/10 ,  G06F12/06

CPC classification number: G11C11/225 ,  G06F11/1068 ,  G06F12/0246 ,  G06F12/06 ,  G11C11/165 ,  G11C11/221 ,  G11C13/0035 ,  G11C13/0059 ,  G11C16/105 ,  G06F2212/1036 ,  G06F2212/7211

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

公开(公告)号：US11853230B2

公开(公告)日：2023-12-26

申请号：US17329989

申请日：2021-05-25

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Sean S. Eilert ,  Bryce D. Cook

IPC: G06F12/14 ,  G06F12/02

CPC classification number: G06F12/1408 ,  G06F12/0238 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.

公开(公告)号：US20230315294A1

公开(公告)日：2023-10-05

申请号：US18329446

申请日：2023-06-05

Applicant: Kioxia Corporation

Inventor： Hideki Yoshida ,  Shinichi Kanno

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7208

Abstract: According to one embodiment, when receiving a write request to designate a first block number and a first logical address from a host, a memory system determines a first location in a first block having the first block number, to which data from the host is to be written, and writes the data from the host to the first location of the first block. The memory system updates a first address translation table managing mapping between logical addresses and in-block physical addresses of the first block, and maps a first in-block physical address indicative of the first location to the first logical address.

公开(公告)号：US11726906B2

公开(公告)日：2023-08-15

申请号：US17130485

申请日：2020-12-22

Applicant: Kioxia Corporation

Inventor： Shinichi Kanno

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/02 ,  G06F2212/1036 ,  G06F2212/222 ,  G06F2212/7201 ,  G06F2212/7209

Abstract: According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.

公开(公告)号：US11670352B1

公开(公告)日：2023-06-06

申请号：US17344820

申请日：2021-06-10

Applicant: Kepler Computing Inc.

Inventor： Christopher B. Wilkerson ,  Sasikanth Manipatruni ,  Rajeev Kumar Dokania ,  Amrita Mathuriya

IPC: G11C11/00 ,  G11C11/16 ,  G06F12/06 ,  G06F11/10 ,  G11C11/22 ,  G11C13/00

CPC classification number: G11C11/165 ,  G06F11/1068 ,  G06F12/06 ,  G11C11/221 ,  G11C11/225 ,  G11C13/0035 ,  G06F2212/1036

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

公开(公告)号：US20230168812A1

公开(公告)日：2023-06-01

申请号：US18103133

申请日：2023-01-30

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Seungjune Jeon ,  Zhenlei Shen

IPC: G06F3/06 ,  G06F12/10 ,  G06F7/58 ,  G06F12/02

CPC classification number: G06F3/0616 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0679 ,  G06F7/588 ,  G06F12/10 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

Abstract: Systems and methods are disclosed including a processing device operatively coupled to memory device. The processing device performs operations comprising responsive to receiving a memory access command, determining a portion of the memory device that is referenced by a logical address specified by the memory access command; determining an endurance factor associated with the portion; and modifying, based on a value derived from the endurance factor, a media management metric associated with the portion of the memory device.

公开(公告)号：US20190243758A1

公开(公告)日：2019-08-08

申请号：US16243124

申请日：2019-01-09

Applicant: FUJITSU LIMITED

Inventor： Kazuya Takeda ,  Yusuke Kurasawa ,  Yusuke Suzuki ,  Norihide KUBOTA ,  Yuji TANAKA ,  Toshio IGA ,  YOSHIHITO KONTA ,  Marino Kajiyama ,  Takeshi WATANABE

IPC: G06F12/0804 ,  G06F12/02

CPC classification number: G06F12/0804 ,  G06F12/0253 ,  G06F2212/1036 ,  G06F2212/1044 ,  G06F2212/2022

Abstract: A storage control device includes a processor that reads out a group write area, in which data blocks are arranged, from a storage medium and store the group write area in a buffer area. The processor releases a part of the payload area for each data block arranged in the first group write area stored in the first buffer area. The part stores invalid data. The processor performs the garbage collection by performing data refilling. The data refilling is performed by moving valid data stored in the payload to fill up a front by using the released part, and updating an offset included in a header stored in a header area at a position indicated by index information corresponding to the moved valid data without changing the position indicated by the index information corresponding to the moved valid data. The header area is included in the data block.

公开(公告)号：US20190196713A9

公开(公告)日：2019-06-27

申请号：US15499877

申请日：2017-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingpei YANG ,  Changho CHOI ,  Rajinikanth PANDURANGAN ,  Vijay BALAKRISHNAN ,  Ramaraj PANDIAN

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/18 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7205

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory to store data and may support a plurality of device streams. A SSD controller may manage reading and writing data to the flash memory, and may store a submission queue and a chunk-to-stream mapper. A flash translation layer may include a receiver to receive a write command, an LBA mapper to map an LBA to a chunk identifier (ID), stream selection logic to select a stream ID based on the chunk ID, a stream ID adder to add the stream ID to the write command, a queuer to place the chunk ID in the submission queue, and background logic to update the chunk-to-stream mapper after the chunk ID is removed from the submission queue.