公开(公告)号：US12066930B2

公开(公告)日：2024-08-20

申请号：US18200975

申请日：2023-05-23

Applicant: Micron Technology, Inc.

Inventor： Byron Harris ,  Daniel Boals ,  Abedon Madril

IPC: G06F12/02 ,  G06F1/30 ,  G06F12/0804 ,  G06F12/0891

CPC classification number: G06F12/0246 ,  G06F1/30 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F2212/7201

Abstract: A journal count reflecting a number of logical-to-physical (L2P) journals written to a non-volatile memory device is maintained, wherein each L2P journal is associated with one or more updates to an L2P address mapping table. In response to determining that the journal count satisfies a threshold criterion, a first section of a plurality of sections of the L2P address mapping table is identified, wherein the plurality of sections of the L2P address mapping table is cached in a volatile memory device. The first section of the L2P address mapping table is written to the non-volatile memory device.

公开(公告)号：US12061557B2

公开(公告)日：2024-08-13

申请号：US18034541

申请日：2021-09-29

Applicant: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.

Inventor： Qinglu Chen

IPC: G06F12/02 ,  G06F12/1027 ,  G06F11/14

CPC classification number: G06F12/1027 ,  G06F12/0238 ,  G06F12/0246 ,  G06F11/1471 ,  G06F2212/7201

Abstract: The present disclosure provides a method for storing an L2P table, including the following steps: detecting the L2P table, in response to detecting update of the L2P table, acquiring a logical block address (LBA) for which a mapping relation is updated in the L2P table; sending the LBA to a journal manager; reading a corresponding physical block address (PBA) in the L2P table according to the received LBA and assembling the LBA and the corresponding PBA into delta data in response to the journal manager receiving the LBA; and saving the delta data and several basic data currently to be saved in the L2P table as a snapshot in a non-volatile memory. The present disclosure further provides a system, a computer device, and a readable storage medium.

公开(公告)号：US20240248840A1

公开(公告)日：2024-07-25

申请号：US18624426

申请日：2024-04-02

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Christopher Joseph Bueb

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0656 ,  G06F3/067 ,  G06F12/063 ,  G06F12/0646 ,  G06F2212/7201 ,  G06F2212/7211

Abstract: A technique to control write operations in a logical partition. For example, a device can receive a user specified write threshold for the logical partition that is hosted on a pool of memory cells shared by a plurality of logical partitions in wear leveling. An accumulated amount of data written into the memory cells according to write requests addressing the logical partition is tracked. In response to the accumulated amount reaches the write threshold, further write requests addressing the logical partition can be blocked, rejected, and/or ignored. For example, the logical partition can be used to buffer data for time shift in playing back content streaming from a server. Write operations for time shift can be limited via the user specified threshold to prevent overuse of the total program erasure budget of the pool of memory cells shared with other logical partitions.

公开(公告)号：US12032960B2

公开(公告)日：2024-07-09

申请号：US17708882

申请日：2022-03-30

Applicant: Infineon Technologies AG

Inventor： Sandeep Vangipuram ,  Glenn Ashley Farrall

IPC: G06F9/30 ,  G06F12/02

CPC classification number: G06F9/30018 ,  G06F9/3004 ,  G06F9/30105 ,  G06F9/30145 ,  G06F12/0238 ,  G06F2212/7201

Abstract: A non-volatile memory (NVM) integrated circuit device includes a processing device and an NVM array of memory cells partitioned into a first physical region and a second physical region. The NVM integrated circuit device also includes a plurality of routing circuits, a first decoder associated with a first routing circuit, and a second decoder associated with a second routing circuit. The NVM integrated circuit device also includes a first programmable register coupled to the plurality of routing circuits, wherein the first programmable register is to store a first multi-bit value, the first multi-bit value programmed by the processing device to configure a first address range associated with the first decoder. The NVM integrated circuit device also includes a second programmable register coupled to the plurality of routing circuits, wherein the second programmable register is to store a second multi-bit value, the second multi-bit value programmed by the processing device to configure a second address range associated with the second decoder.

公开(公告)号：US12014792B2

公开(公告)日：2024-06-18

申请号：US18108302

申请日：2023-02-10

Applicant: Micron Technology, Inc.

Inventor： Mark D. Ingram ,  Todd Jackson Plum ,  Scott E. Schaefer ,  Aaron P. Boehm ,  Scott D. Van De Graaff

IPC: G11C29/44 ,  G06F12/02 ,  G11C29/12

CPC classification number: G11C29/4401 ,  G06F12/0238 ,  G11C29/12005 ,  G11C29/12015 ,  G06F2212/7201 ,  G06F2212/7211 ,  G11C2207/2254

Abstract: Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

公开(公告)号：US12013779B2

公开(公告)日：2024-06-18

申请号：US17991133

申请日：2022-11-21

Applicant: KIOXIA CORPORATION

Inventor： Daisuke Hashimoto

IPC: G06F12/02 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F12/0246 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0643 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0638 ,  G06F11/1456 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7208 ,  Y02D10/00

Abstract: A storage system includes a host including a processor and a memory unit, and a storage device including a controller and a non-volatile memory unit. The processor is configured to output a write command, write data, and size information of the write data, to the storage device, the write command that is output not including a write address. The controller is configured to determine a physical write location of the non-volatile memory unit in which the write data are to be written, based on the write command and the size information, write the write data in the physical write location of the non-volatile memory unit, and output the physical write location to the host. The processor is further configured to generate, in the memory unit, mapping information between an identifier of the write data and the physical write location.

公开(公告)号：US20240193095A1

公开(公告)日：2024-06-13

申请号：US17758335

申请日：2022-03-17

Applicant: Micron Technology, Inc.

Inventor： Liping Xu ,  Zhen Gu ,  Qingyuan Wang

IPC: G06F12/1009 ,  G06F12/1045

CPC classification number: G06F12/1009 ,  G06F12/1054 ,  G06F2212/7201

Abstract: Methods, systems, and devices for a sorted change log for physical page table compression are described. A mapping between a logical address and a physical address may be stored in a change log buffer. The mapping may be stored at a location of the change log buffer based on the logical address of the mapping relative to logical addresses of other mappings stored in the change log buffer. Based on storing mappings in the change log buffer based on logical addresses of the mappings, a set of mappings in the change log may include a set of sequentially-indexed logical addresses. A compressed entry for a logical-to-physical table may be generated based on the set of mappings.

公开(公告)号：US20240184695A1

公开(公告)日：2024-06-06

申请号：US18442248

申请日：2024-02-15

Applicant: Micron Technology, Inc.

Inventor： Byron Harris ,  Daniel Boals ,  Abedon Madril

IPC: G06F12/0802 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679 ,  G06F2212/60 ,  G06F2212/7201

Abstract: A total count for an address mapping table is maintained, wherein the total count reflects a total number of updates to the address mapping table, and wherein the address mapping table comprises a plurality of sections. Respective section counts for the plurality of sections are maintained, wherein each respective section count reflects a total number of updates to a corresponding section. It is determined that the total count for the address mapping table satisfies a threshold criterion. A first section of the plurality of sections with a highest section count is identified based on the respective section counts. The first section of the address mapping table is written to a non-volatile memory device.

公开(公告)号：US11997163B2

公开(公告)日：2024-05-28

申请号：US17404424

申请日：2021-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Harry Rogers ,  Sompong Paul Olarig ,  Ramdas P. Kachare

IPC: G06F15/167 ,  G06F12/02 ,  G06T1/20 ,  H04L61/2596 ,  H04L67/1097

CPC classification number: H04L67/1097 ,  G06F12/0246 ,  G06T1/20 ,  H04L61/2596 ,  G06F2212/7201

Abstract: A method of transferring data to an end user via a content distribution network using an nonvolatile memory express over fabrics (NVMe-oF) device, the method including receiving a read request at the NVMe-oF device, translating a logical address corresponding to the data to a physical address, fetching the data from a flash storage of the NVMe-oF device, processing the data with a GPU that is either embedded in the NVMe-oF device, or on a same chassis as the NVMe-oF device, and transferring the data.

公开(公告)号：US11995003B2

公开(公告)日：2024-05-28

申请号：US17516007

申请日：2021-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heng Zhang ,  Yinxin Zhao

IPC: G06F12/1045 ,  G06F12/02 ,  G06F12/0868

CPC classification number: G06F12/1054 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0868 ,  G06F2212/7201

Abstract: A method of data caching includes; determining a process corresponding to a read request communicated from a host, obtaining historical access information for the process according to historical process information stored in a cache, wherein the historical process information includes at least one of historical access information for the process and heat information for one or more regions historically accessed by the process, determining a first region historically accessed by the process according to the historical access information, such that heat information for the first region satisfies a first preset condition, and loading a physical address for the first region from a storage device to the cache.