公开(公告)号：US11948810B2

公开(公告)日：2024-04-02

申请号：US15906689

申请日：2018-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Chao Yin ,  Yuling Chiu ,  Yu-Lung Yang ,  Hung-Bin Lin

IPC: H01L21/67

CPC classification number: H01L21/67017 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/6719 ,  H01L21/67196 ,  H01L21/67126 ,  H01L21/67201

Abstract: A vacuum apparatus includes process chambers, and a transfer chamber coupled to the process chambers. The transfer chamber includes one or more vacuum ports, thorough which a gas inside the transfer chamber is exhausted, and vent ports, from which a vent gas is supplied. The one or more vacuum ports and the vent ports are arranged such that air flows from at least one of the vent ports to the one or more vacuum ports are line-symmetric with respect to a center line of the transfer chamber.

公开(公告)号：US20240055285A1

公开(公告)日：2024-02-15

申请号：US18494710

申请日：2023-10-25

Applicant: Lam Research Corporation

Inventor： Edward Augustyniak ,  David French ,  Sunil Kapoor ,  Yukinori Sakiyama ,  George Thomas

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/687

CPC classification number: H01L21/67288 ,  H01L21/67259 ,  H01L21/67253 ,  H01L21/67207 ,  H01L21/67069 ,  H01L21/67167 ,  H01J37/32183 ,  H01L21/68771 ,  H01J37/32385 ,  H01J37/32935 ,  H01J37/32577 ,  H01L21/67201 ,  H01J37/32715 ,  H01J2237/3321

Abstract: A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and another circuit that provides a high frequency RF signal. The system includes an output circuit and the stations. The output circuit combines the low frequency RF signal and the high frequency RF signal to generate a plurality of combined RF signals for the stations. Amount of low frequency power delivered to one of the stations depends on wafer bow, such as non-flatness of a wafer. A bowed wafer decreases low frequency power delivered to the station in a multi-station chamber with a common RF source. A shunt inductor is coupled in parallel to each of the stations to increase an amount of current to the station with a bowed wafer. Hence, station power becomes less sensitive to wafer bow to minimize wafer bowing.

公开(公告)号：US20240038559A1

公开(公告)日：2024-02-01

申请号：US17876014

申请日：2022-07-28

Applicant: Brillian Network & Automation Integrated System Co., Ltd.

Inventor： YI-JUN GU

IPC: H01L21/673 ,  H01L21/67

CPC classification number: H01L21/673 ,  H01L21/67201 ,  H01L21/67017

Abstract: A load port and a multi-use carrier are provided. The load port includes a carrying board, two gas-inlet nozzles disposed on the carrying board, and two gas-outlet nozzles disposed on the carrying board. Each of the two gas-inlet nozzles has a shared gas-inlet channel. Each of the two gas-outlet nozzles has a first gas-outlet channel and a second gas-outlet channel that is spaced apart from the first gas-outlet channel. The shared gas-inlet channels of the two gas-inlet nozzles are selectively cooperated with the first gas-outlet channels of the two gas-outlet nozzles so as to be jointly configured to spatially communicate with a first wafer cassette. The shared gas-inlet channels of the two gas-inlet nozzles are selectively cooperated with the second gas-outlet channels of the two gas-outlet nozzles so as to be jointly configured to spatially communicate with a second wafer cassette.

公开(公告)号：US11885023B2

公开(公告)日：2024-01-30

申请号：US16584283

申请日：2019-09-26

Applicant: ASM IP Holding B.V.

Inventor： Shiva K. T. Rajavelu Muralidhar ,  Sam Kim ,  Jeffrey Barrett Robinson ,  James King Wilson, Jr. ,  Ninad Vijay Sonje

IPC: C23C16/46 ,  H01L21/67 ,  H01L21/687 ,  C23C16/458 ,  C23C16/44

CPC classification number: C23C16/466 ,  C23C16/4411 ,  C23C16/4586 ,  H01L21/67201 ,  H01L21/68757

Abstract: A substrate retaining apparatus, a load lock assembly comprising the substrate retaining apparatus, and a system including the substrate retaining apparatus are disclosed. The substrate retaining apparatus can include at least one sidewall and one or more heat shields. One or more of the at least one sidewall can include a cooling fluid conduit to facilitate cooling of substrates retained by the substrate retaining apparatus. Additionally or alternatively, one or more of the at least one sidewall can include a gas conduit to provide gas to a surface of a retained substrate.

公开(公告)号：US11860528B2

公开(公告)日：2024-01-02

申请号：US17129077

申请日：2020-12-21

Applicant: Applied Materials, Inc.

Inventor： Ribhu Gautam ,  Vibhu Jindal ,  Sanjay Bhat ,  Praveen Kumar Choragudi ,  Vinodh Ramachandran ,  Arun Rengaraj

IPC: H01L21/67 ,  G03F1/24 ,  H01L21/687 ,  B65G47/90 ,  C23C14/06 ,  C23C14/56 ,  C23C14/58 ,  C23C14/35

CPC classification number: G03F1/24 ,  B65G47/90 ,  C23C14/0641 ,  C23C14/35 ,  C23C14/566 ,  C23C14/568 ,  C23C14/5806 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67207 ,  H01L21/68707 ,  H01L21/68742 ,  H01L21/68764

Abstract: Substrate processing systems or platforms and methods configured to process substrates including of extreme ultraviolet (EUV) mask blanks are disclosed. Systems or platforms provide a small footprint, high throughput of substrates and minimize defect generation. The substrate processing system platform comprises a single central transfer chamber, a single transfer robot, a substrate flipping fixture, and processing chambers are positioned around the single central transfer chamber.

公开(公告)号：US20230335414A1

公开(公告)日：2023-10-19

申请号：US18187396

申请日：2023-03-21

Applicant: Brooks Automation US, LLC

Inventor： Christopher HOFMEISTER ,  Martin R. ELLIOTT ,  Alexander KRUPYSHEV ,  Joseph HALLISEY ,  Joseph A. KRAUS ,  William FOSNIGHT ,  Craig J. CARBONE ,  Jeffrey C. BLAHNIK ,  Ho Yin Owen FONG

IPC: H01L21/67 ,  F27B17/00

CPC classification number: H01L21/67017 ,  H01L21/67201 ,  H01L21/6719 ,  H01L21/67098 ,  F27B17/0025

Abstract: A semiconductor processing tool is disclosed, the tool having a frame forming at least one chamber with an opening and having a sealing surface around a periphery of the opening, a door configured to interact with the sealing surface for sealing the opening, the door having sides perpendicular to the door sealing surface and perpendicular to a transfer plane of a substrate, and at least one drive located on the frame to a side of at least one of the sides that are substantially perpendicular to the door sealing surface and substantially perpendicular to the transfer plane of the substrate, the drive having actuators located at least partially in front of the sealing surface and the actuators being coupled to one of the sides of the door for moving the door from a sealed position. The at least one drive is located outside of a substrate transfer zone.

公开(公告)号：US20230298918A1

公开(公告)日：2023-09-21

申请号：US17955758

申请日：2022-09-29

Applicant: Kokusai Electric Corporation

Inventor： Hiroshi ASHIHARA ,  Yuji TAKEBAYASHI

IPC: H01L21/677 ,  H01L21/687 ,  H01L21/67

CPC classification number: H01L21/67712 ,  H01L21/67745 ,  H01L21/68764 ,  H01L21/67201

Abstract: There is provided a technique that includes: at least one process chamber in which at least one substrate is processed; a mounting stage configured to be capable of mounting the at least one substrate on the mounting stage; a transport chamber including a conveyor configured to be capable of holding the mounting stage at least two places in a vertical direction and transporting the mounting stage; and a controller configured to be capable of performing a transport control of the conveyor in the transport chamber.

公开(公告)号：US11756813B2

公开(公告)日：2023-09-12

申请号：US17476890

申请日：2021-09-16

Applicant: SEMES CO., LTD.

Inventor： Yong Seok Jang ,  In Kyu Park

IPC: H01L21/677 ,  H01L21/67 ,  H01L21/68 ,  H01L21/673

CPC classification number: H01L21/67201 ,  H01L21/67115 ,  H01L21/67265 ,  H01L21/67389 ,  H01L21/67745 ,  H01L21/68

Abstract: Disclosed is a substrate treating apparatus. The substrate treating apparatus includes an index unit including a load pot, in which a container is seated, and an index chamber connected to the load pot, and a process executing unit having a load lock chamber connected to the index chamber and a process chamber that treats a substrate transferred to the load lock chamber, the index unit further includes an alignment unit provided in the index chamber and that aligns a substrate type sensor transferred to the process chamber.

公开(公告)号：US11742229B2

公开(公告)日：2023-08-29

申请号：US17553658

申请日：2021-12-16

Applicant: Lam Research Corporation

Inventor： Jacob L. Hiester ,  Richard Blank ,  Peter Thaulad ,  Paul Konkola

IPC: H01L21/67 ,  H01L21/687 ,  H01L21/68 ,  H01L21/677 ,  H01J37/32 ,  H01L21/66 ,  H01L21/683

CPC classification number: H01L21/67259 ,  H01J37/32724 ,  H01L21/67161 ,  H01L21/67201 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/67742 ,  H01L21/67748 ,  H01L21/68 ,  H01L21/681 ,  H01L21/68742 ,  H01L21/68764 ,  H01L21/68771 ,  H01L22/20 ,  H01J2237/2446 ,  H01J2237/24578 ,  H01J2237/334 ,  H01J2237/3321 ,  H01L21/6831

Abstract: A method for calibration including determining a temperature induced offset in a pedestal of a process module under a temperature condition for a process. The method includes delivering a wafer to the pedestal of the process module by a robot, and detecting an entry offset. The method includes rotating the wafer over the pedestal by an angle. The method includes removing the wafer from the pedestal by the robot and measuring an exit offset. The method includes determining a magnitude and direction of the temperature induced offset using the entry offset and exit offset.

公开(公告)号：US11715659B2

公开(公告)日：2023-08-01

申请号：US17836703

申请日：2022-06-09

Applicant: PICO & TERA CO., LTD. ,  Bum Je Woo

Inventor： Bum Je Woo

IPC: H01L21/673 ,  H01L21/677 ,  H01L21/67

CPC classification number: H01L21/67393 ,  H01L21/6773 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/67376 ,  H01L21/67386

Abstract: Proposed is an EFEM configured to perform wafer transfer between a wafer storage device and process equipment. More particularly, proposed is an EFEM that prevents harmful gases inside a transfer chamber in which wafer transfer is performed from escaping out of the EFEM.