Abstract:
A process of forming a thermal interface material structure includes selectively masking a putty pad that includes ultraviolet (UV) curable cross-linkers to form a masked putty pad. The masked putty pad has a first area that is exposed and a second area that is masked. The process also includes exposing the masked putty pad to UV light to form a selectively cross-linked putty pad. The process includes disposing the selectively cross-linked putty pad between an electrical component and a heat spreader to form an assembly. The process further includes compressing the assembly to form a thermal interface material structure that includes a selectively cross-linked thermal interface material.
Abstract:
The present invention relates to CNT filled polymer composite system possessing a high thermal conductivity and high temperature stability so that it is a highly thermally conductive for use in 3D and 4D integration for joining device sub-laminate layers. The CNT/polymer composite also has a CTE close to that of Si, enabling a reduced wafer structural warping during high temperature processing cycling. The composition is tailored to be suitable for coating, curing and patterning by means conventionally known in the art.
Abstract:
A method for connecting components involves providing an arrangement of at least two components each containing at least one metallic contact surface and a metallic sintering agent in the form of a metallic solid body having metal oxide surfaces arranged between the components and pressuring sintering the arrangement whereby metal oxide surfaces of the metallic sintering agent and the metallic contact surfaces of the components each form a joint contact surface. The pressure sintering is carried out in an atmosphere containing at least one oxidizable compound and/or the metal oxide surfaces are provided with at least one oxidizable organic compound before formation of the corresponding joint contact surface.
Abstract:
Methods, systems, and apparatuses that assist with cooling semiconductor packages, such as multi-chip packages (MCPs) are described. A semiconductor package includes a component on a substrate. The component can include one or more semiconductor dies. The package can also include a multi-reference integrated heat spreader (IHS) solution (also referred to as a smart IHS solution), where the smart IHS solution includes a smart IHS lid. The smart IHS lid includes a cavity formed in a central region of the smart lid. The smart IHS lid can be on the component, such that the cavity corresponds to the component. A first thermal interface material layer (TIM-layer 1) can be on the component. An individual IHS lid (IHS slug) can be on the TIM-layer 1. The IHS slug can be inserted into the cavity. Furthermore, an intermediate thermal interface material layer (TIM-1A layer) can be between the IHS slug and the cavity.
Abstract:
A semiconductor device includes a substrate and a semiconductor element mounted on the top surface of the substrate. On the top surface of the substrate, one or more pads are disposed outside the mounted semiconductor element when seen in a plan view. Then, a protrusion is disposed on each of the pads. A heat sink is disposed above the semiconductor element and the protrusions, and then bonded to the substrate by an adhesive provided between the heat sink and the substrate. The adhesive is provided in such a manner as to be in contact with the protrusions on the substrate.
Abstract:
A method of manufacturing a semiconductor structure, comprising: receiving a first substrate including a first surface, a second surface opposite to the first surface and a plurality of conductive bumps disposed over the first surface; receiving a second substrate; disposing an adhesive over the first substrate or the second substrate; heating the adhesive in a first ambiance; bonding the first substrate with the second substrate by applying a force of less than about 10,000N upon the first substrate or the second substrate and heating the adhesive in a second ambiance; and thinning down a thickness of the first substrate from the second surface.
Abstract:
Provided is a method for manufacturing a semiconductor package, which includes providing a first substrate, providing, over the first substrate, a second substrate including an active region in which a semiconductor element is disposed and a periphery region surrounding the active region, providing an adhesive membrane between the first and second substrates, and mounting the second substrate on the first substrate, wherein the mounting of the second substrate includes aligning the second substrate on the first substrate by using an alignment member protruding from the periphery region of the second substrate.
Abstract:
A method of manufacturing a semiconductor structure includes providing a first wafer including a surface, removing some portions of the first wafer over the surface to form a plurality of recesses extended over at least a portion of the surface of the first wafer, providing a second wafer, and disposing the second wafer over the surface of the first wafer.
Abstract:
A semiconductor device has a semiconductor element provided with a functional surface on which a functional circuit is formed and with a back surface facing in the opposite direction to the functional surface, while also having a lead supporting the semiconductor element and electrically connected to the semiconductor element, and a resin package covering at least a portion of the semiconductor element and the lead. The semiconductor element has a functional surface side electrode formed on the functional surface and equipped with a functional surface side raised part that projects in the direction in which the functional surface faces. The functional surface side raised part of the functional surface side electrode is joined to the lead by solid state bonding.