公开(公告)号：US20120089984A1

公开(公告)日：2012-04-12

申请号：US12900667

申请日：2010-10-08

Applicant: Etai Adar ,  Srinivasan Ramani ,  Eric F. Robinson ,  Thuong Q. Truong

Inventor： Etai Adar ,  Srinivasan Ramani ,  Eric F. Robinson ,  Thuong Q. Truong

IPC: G06F9/46 ,  G06F13/24

CPC classification number: G06F11/3466 ,  G06F9/4812 ,  G06F9/5077 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88

Abstract: Counter registers are shared among multiple threads executing on multiple processor cores. An event within the processor core is selected. A multiplexer in front of each of a number of counters is configured to route the event to a counter. A number of counters are assigned for the event to each of a plurality of threads running for a plurality of applications on a plurality of processor cores, wherein each of the counters includes a thread identifier in the interrupt thread identification field and a processor identifier in the processor identification field. The number of counters is configured to have a number of interrupt thread identification fields and a number of processor identification fields to identify a thread that will receive a number of interrupts.

Abstract translation: 计数器寄存器在多个处理器核心上执行的多个线程之间共享。 选择处理器核心内的一个事件。 在多个计数器中的每一个之前的多路复用器被配置为将事件路由到计数器。 为多个处理器核心上的多个应用程序运行的多个线程中的每个线程分配了多个计数器，其中每个计数器在中断线程标识字段中包括线程标识符，以及处理器标识符 处理器识别字段。 计数器的数量被配置为具有多个中断线程标识字段和多个处理器标识字段以标识将接收多个中断的线程。

公开(公告)号：US20120079235A1

公开(公告)日：2012-03-29

申请号：US12890653

申请日：2010-09-25

Applicant: Ravishankar Iyer ,  Sadagopan Srinivasan ,  Li Zhao ,  Rameshkumar G. Illikkal

Inventor： Ravishankar Iyer ,  Sadagopan Srinivasan ,  Li Zhao ,  Rameshkumar G. Illikkal

IPC: G06F9/305 ,  G06F9/46

CPC classification number: G06F9/4881 ,  G06F9/5027 ,  G06F11/3409 ,  G06F11/3433 ,  G06F12/084 ,  G06F2201/88 ,  G06N5/02 ,  Y02D10/13 ,  Y02D10/22 ,  Y02D10/34

Abstract: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.

Abstract translation: 描述了在异构多处理器计算平台中调度应用程序的方法和装置。 在一个实施例中，处理器的多个处理器核的性能（例如，执行性能和/或功耗性能）的信息被存储（并被跟踪）在计数器和/或表中。 处理器中的逻辑根据存储的信息确定哪个处理器内核应该执行应用程序。 还要求和公开其它实施例。

公开(公告)号：US08140761B2

公开(公告)日：2012-03-20

申请号：US12630946

申请日：2009-12-04

Applicant: Kattamuri Ekanadham ,  Il Park

Inventor： Kattamuri Ekanadham ,  Il Park

IPC: G06F12/00

CPC classification number: G06F12/0897 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/88

Abstract: An event tracking hardware engine having N (≧2) caches is invoked when an event of interest occurs, using a corresponding key. The event tracking engine stores a cumulative number of occurrences for each one of the different kinds of events, and searches in the N caches for an entry for the key. When an entry for the key is found, the engine increments the number of occurrences if no overflow of the cumulative number of occurrences would occur. However, if the incrementing would cause overflow, then instead of incrementing the cumulative number of occurrences, the engine promotes the entry for the event of interest to a next higher cache.

Abstract translation: 使用对应的密钥，当感兴趣的事件发生时，调用具有N（≥2）个高速缓存的事件跟踪硬件引擎。 事件跟踪引擎存储每种不同类型事件的累积发生次数，并在N个高速缓存中搜索密钥的条目。 当找到密钥的条目时，如果没有发生累计发生次数的溢出，引擎会增加出现次数。 然而，如果增量会导致溢出，那么引擎不会增加累积的出现次数，而是为下一个更高的缓存感兴趣的事件提升条目。

公开(公告)号：US08131970B2

公开(公告)日：2012-03-06

申请号：US12427609

申请日：2009-04-21

Applicant: Thomas Martin Conte ,  Andrew Wolfe

Inventor： Thomas Martin Conte ,  Andrew Wolfe

IPC: G06F12/00

CPC classification number: G06F12/084 ,  G06F8/41 ,  G06F11/3466 ,  G06F2201/88 ,  G06F2201/885

Abstract: Techniques a generally described for creating a compiler determined map for the allocation of memory space within a cache. An example computing system is disclosed having a multicore processor with a plurality of processor cores. At least one cache may be accessible to at least two of the plurality of processor cores. A compiler determined map may separately allocate a memory space to threads of execution processed by the processor cores.

Abstract translation: 一般描述用于创建用于缓存内存空间分配的编译器确定的映射的技术。 公开了一种示例计算系统，其具有具有多个处理器核心的多核处理器。 多个处理器核中的至少两个可以访问至少一个高速缓存。 编译器确定的映射可以分别将内存空间分配给由处理器核处理的执行线程。

公开(公告)号：US20120054375A1

公开(公告)日：2012-03-01

申请号：US12869591

申请日：2010-08-26

Applicant: Richard L. Arndt ,  Karthick Rajamani ,  Jeffrey A. Stuecheli

Inventor： Richard L. Arndt ,  Karthick Rajamani ,  Jeffrey A. Stuecheli

IPC: G06F3/00 ,  G06F12/08

CPC classification number: G06F11/3485 ,  G06F2201/88

Abstract: According to one aspect of the present disclosure a method and technique for monitoring memory access is disclosed. The method includes monitoring, by a plurality of memory controllers, access to a memory unit, wherein each memory controller is associated with a different range of memory addresses of the memory unit, and wherein each memory controller monitors access for its associated range of memory addresses. The method also includes updating an incrementor with access data corresponding to accesses to the memory unit, wherein each memory controller updates the access data based on access of its associated range of memory addresses. The method further includes storing, by each respective memory controller, the updated access data in a cache corresponding to the respective range of memory addresses and, responsive to the updated access data for a respective range of memory addresses exceeding a threshold, storing the access data for the respective range of memory addresses in memory unit.

Abstract translation: 根据本公开的一个方面，公开了一种用于监视存储器访问的方法和技术。 该方法包括通过多个存储器控制器监视对存储器单元的访问，其中每个存储器控制器与存储器单元的存储器地址的不同范围相关联，并且其中每个存储器控制器监视对其相关联的存储器地址范围的访问 。 该方法还包括使用与对存储器单元的访问相对应的访问数据来更新增量器，其中每个存储器控制器基于其相关联的存储器地址范围的访问来更新访问数据。 该方法还包括由每个相应的存储器控​​制器将更新的访问数据存储在与存储器地址的相应范围相对应的高速缓存中，并且响应于对于超过阈值的存储器地址的相应范围的更新的访问数据，存储访问数据 对于存储器单元中的各个存储器地址范围。

公开(公告)号：US20120046912A1

公开(公告)日：2012-02-23

申请号：US12858497

申请日：2010-08-18

Applicant: Venkat Rajeev Indukuru ,  Alexander Erik Mericas

Inventor： Venkat Rajeev Indukuru ,  Alexander Erik Mericas

IPC: G06F15/00

CPC classification number: G06F11/348 ,  G06F2201/88

Abstract: A performance monitor including a saturating counter provides a relative measure of event frequency without requiring a minimum polling rate or periodic reset to avoid or account for counter overflow. The saturating counter is incremented upon detection of an event and decremented if an event is not detected within a predetermined period. The period of detecting may be programmable and may be determined by real time clock, processor or instruction cycles. Multiple event types may be selected from for detection and input to a single counter, or alternatively multiple event counters may be provided for various event types. The saturating counter may additionally be periodically reset in a selected operating mode, in combination with the decrementing action performed on the counter.

Abstract translation: 包括饱和计数器的性能监视器提供事件频率的相对度量，而不需要最小轮询速率或周期性复位来避免或考虑计数器溢出。 饱和计数器在检测到事件时增加，并且如果在预定时间段内未检测到事件，则递减计数器。 检测周期可以是可编程的，并且可以通过实时时钟，处理器或指令周期来确定。 可以选择多个事件类型用于检测和输入到单个计数器，或者可以为各种事件类型提供多个事件计数器。 饱和计数器可以另外在所选择的操作模式中周期性地复位，并结合在计数器上执行的递减动作。

公开(公告)号：US08117376B2

公开(公告)日：2012-02-14

申请号：US12007330

申请日：2008-01-09

Applicant: Masateru Hemmi

Inventor： Masateru Hemmi

IPC: G06F12/02

CPC classification number: G06F11/2089 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/108 ,  G06F11/1088 ,  G06F11/1662 ,  G06F11/2094 ,  G06F2201/88 ,  G06F2211/109

Abstract: Proposed are a storage system and its control method capable of dealing with the unique problems that arise when using a nonvolatile memory as the memory device while effectively preventing performance deterioration. This storage system is provided with a plurality of memory modules having one or more nonvolatile memory chips, and a controller for controlling the reading and writing of data from and in each memory module. The memory module decides the nonvolatile memory chip to become a copy destination of data stored in the nonvolatile memory when a failure occurs in the nonvolatile memory chip of a self memory module, and copies the data stored in the failed nonvolatile memory chip to the nonvolatile memory chip decided as the copy destination.

Abstract translation: 提出了一种存储系统及其控制方法，能够处理在使用非易失性存储器作为存储装置时产生的独特问题，同时有效地防止性能恶化。 该存储系统设置有具有一个或多个非易失性存储器芯片的多个存储器模块，以及用于控制来自每个存储器模块中和/或每个存储器模块中的数据的读取和写入的控制器。 当在自身存储器模块的非易失性存储器芯片中发生故障时，存储器模块决定非易失性存储器芯片成为存储在非易失性存储器中的数据的复制目的地，并将存储在故障非易失性存储器芯片中的数据复制到非易失性存储器 芯片决定为复制目的地。

公开(公告)号：US08112250B2

公开(公告)日：2012-02-07

申请号：US12263597

申请日：2008-11-03

Applicant: Michael S. Floyd ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

Inventor： Michael S. Floyd ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

IPC: G06F19/00

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/88 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/34

Abstract: Semiconductor device circuits and methods are provided for adjusting core processor performance and energy-efficiency based on usage metrics. Metric detection, performance state selection, and adjustment are done in digital logic hardware without intervening input from system software or firmware, thus greatly speeding the processor performance adjustment. Mapping usage and state information to desired processor power-performance states is also provided in circuitry rather than firmware or power control software. The mapping values may be programmable software or firmware, but detection, selection, and adjustment occur automatically in hardware without intervening input from firmware or software.

Abstract translation: 提供了半导体器件电路和方法，用于根据使用度量来调整核心处理器的性能和能量效率。 在数字逻辑硬件中进行公制检测，性能状态选择和调整，无需系统软件或固件的中间输入，从而大大加快了处理器的性能调整。 电路而不是固件或电源控制软件也提供了将使用和状态信息映射到所需的处理器电源性能状态。 映射值可以是可编程软件或固件，但是检测，选择和调整会在硬件中自动进行，而无需固件或软件的输入。

公开(公告)号：US08108874B2

公开(公告)日：2012-01-31

申请号：US11753479

申请日：2007-05-24

Applicant: Takeshi Ogasawara ,  Hideaki Komatsu

Inventor： Takeshi Ogasawara ,  Hideaki Komatsu

IPC: G06F9/46 ,  G06F15/173

CPC classification number: G06F9/505 ,  G06F11/3419 ,  G06F2201/88 ,  G06F2209/5018 ,  G06F2209/504 ,  G06F2209/508 ,  Y02D10/22

Abstract: Variations of waiting times of requests for services handled by a processor are minimized. In response to the processor receiving a request for a service, an arrival time of the request for the service is recorded and added to a total arrival time for all requests for the service, and a counter of a number of waiting requests for the service is incremented. In response to the processor processing the request, the arrival time of the request is subtracted from the total arrival time, and the counter is decremented. In either case, an average waiting time of requests for the service is determined, a history of the average waiting times is maintained, and the variation within this history is determined. Where the variation is greater than a threshold, processor resources are adjusted to minimize variations within waiting times of requests for all the services handled by the processor.

Abstract translation: 由处理器处理的服务请求的等待时间的变化最小化。 响应于处理器接收到对服务的请求，对服务请求的到达时间被记录并添加到对于服务的所有请求的总到达时间，并且对服务的等待请求的数量的计数器是 递增 响应于处理器处理请求，从总到达时间减去请求的到达时间，并且计数器递减。 在任一情况下，确定服务请求的平均等待时间，维持平均等待时间的历史，并且确定该历史中的变化。 在变化大于阈值的情况下，调整处理器资源以使处理器处理的所有服务的请求的等待时间内的变化最小化。

公开(公告)号：US08108179B2

公开(公告)日：2012-01-31

申请号：US12041304

申请日：2008-03-03

Applicant: Tara Astigarraga ,  William E. Atherton ,  Michael E. Browne

Inventor： Tara Astigarraga ,  William E. Atherton ,  Michael E. Browne

IPC: G06F12/00

CPC classification number: G11C16/349 ,  G06F11/008 ,  G06F11/3466 ,  G06F12/0246 ,  G06F2201/88

Abstract: Disclosed are a method, electronic device, and computer readable medium for determining an end-of-life stage of the flash memory. The method includes detecting at least one life cycle event associated with a flash memory residing on an electronic device. A counter that is associated with the life cycle event is then incremented. Based on the counter, a total number of occurrences for the one life cycle event is determined. The total number of occurrences for the at least one given threshold is also determined. A current life cycle stage of the flash memory is identified based at least in part on determining if the total number of occurrences exceeds at least one given threshold. The life cycle stage is associated with the at least one given threshold. A user is then notified of the life cycle state of the flash memory.