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    Multiport series memory component
    211.
    发明授权
    Multiport series memory component 失效
    多端口系列存储器组件

    公开(公告)号：US5598554A

    公开(公告)日：1997-01-28

    申请号：US470989

    申请日：1995-06-06

    Applicant: Daniel Litaize ,  Jean-Claude Salinier ,  Abdelaziz Mzoughi ,  Fatima-Zahra Elkhlifi ,  Mustapha Lalam ,  Pascal Sainrai

    Inventor： Daniel Litaize ,  Jean-Claude Salinier ,  Abdelaziz Mzoughi ,  Fatima-Zahra Elkhlifi ,  Mustapha Lalam ,  Pascal Sainrai

    IPC: G06F12/08 ,  G06F15/80 ,  G11C7/10 ,  G06F9/00 ,  G06F9/44

    CPC classification number: G06F12/0813 ,  G06F15/8015 ,  G11C7/1036

    Abstract: A multiport series memory component for a multiprocessor system comprising an integrated circuit having a random access memory of a predetermined width corresponding to a block of information, an assembly of shift registers each of which has a size corresponding to the width of the memory unit, an internal parallel bus connecting the access of the memory unit to the shift registers, a shift register slection logic for validating the link on the internal bus between the memory unit and a predetermined shift register, and an assembly of extrnal input/output pins for the input of addresses to the memory unit for the input and validation of transfer commands in reading and writing of a block of information between the memory unit and the shift registers, for the input of a clock signal to each shift register, for bit-by-bit input of a block of information to each shift register and for the bit by bit output of a block of information from each shift register.

    Abstract translation: 一种用于多处理器系统的多端口系列存储器组件，包括具有对应于信息块的预定宽度的随机存取存储器的集成电路，移位寄存器的组合具有与存储器单元的宽度相对应的尺寸， 内部并行总线将存储器单元的访问连接到移位寄存器，用于验证存储器单元和预定移位寄存器之间的内部总线上的链路的移位寄存器选择逻辑，以及用于输入的外部输入/输出引脚的组合 的地址提供给存储器单元，用于输入和确认在存储器单元和移位寄存器之间读取和写入信息块的传送命令，用于向每个移位寄存器输入时钟信号，用于逐位 向每个移位寄存器输入信息块，并从每个移位寄存器逐位输出信息块。

    Memory architecture and devices, systems and methods utilizing the same
    212.
    发明授权
    Memory architecture and devices, systems and methods utilizing the same 失效
    内存架构和使用其的设备，系统和方法

    公开(公告)号：US5568431A

    公开(公告)日：1996-10-22

    申请号：US531755

    申请日：1995-09-21

    Applicant: G. R. Mohan Rao

    Inventor： G. R. Mohan Rao

    IPC: G11C11/401 ,  G06F3/153 ,  G09G5/38 ,  G09G5/39 ,  G11C7/00 ,  G11C7/10

    CPC classification number: G11C7/1036

    Abstract: A memory 200 is provided including a plurality of arrays 202 of memory cells 203. A plurality of registers 211 are also provided, each register 211 for exchanging parallel bits of data with a corresponding one of the arrays 202. Data transfer circuitry 210, 213 is included for transferring parallel bits of data from any selected one of the arrays 202 through the corresponding register 211 to any other selected one of the arrays 202 through the corresponding register 211.

    Abstract translation: 提供存储器200，其包括存储器单元203的多个阵列202.还提供多个寄存器211，每个寄存器211用于与阵列202中的相应一个数据交换数据的并行位。数据传送电路210,213是 包括用于通过相应的寄存器211将阵列202中的任何一个阵列202的数据的并行位通过相应的寄存器211传送到阵列202中的任何其他选定的数据。

    Semiconductor memory device having a coincidence detection circuit and its test method
    213.
    发明授权
    Semiconductor memory device having a coincidence detection circuit and its test method 失效
    具有重合检测电路的半导体存储器件及其测试方法

    公开(公告)号：US5521870A

    公开(公告)日：1996-05-28

    申请号：US354086

    申请日：1994-12-06

    Applicant: Toru Ishikawa

    Inventor： Toru Ishikawa

    IPC: G01R31/28 ,  G11C7/10 ,  G11C11/401 ,  G11C11/413 ,  G11C29/00 ,  G11C29/32 ,  G11C29/34 ,  G11C29/38 ,  G11C11/40

    CPC classification number: G11C7/1036 ,  G11C29/32 ,  G11C29/38 ,  G11C2029/4002

    Abstract: A semiconductor memory device includes a plurality of memory blocks, a write circuit for writing data into the memory blocks, a read circuit for reading data from the memory blocks, a plurality of serial registers, each of which is connected to the corresponding memory block to output serially a plurality of data read from the memory block, a plurality of switches, each of which is arranged between two adjacent ones of the serial registers to connect the serial registers in series, and a coincidence detection circuit for detecting a coincidence of data outputted from a final serial register arranged at a final end of the serial registers connected by the switches with data outputted from a serial register arranged immediately before the final serial register.

    Abstract translation: 半导体存储器件包括多个存储块，用于将数据写入存储块的写入电路，用于从存储块读取数据的读取电路，多个串行寄存器，每个串行寄存器连接到相应的存储器块 输出从存储块读取的多个数据，多个开关，每个开关布置在串联寄存器的两个相邻串行寄存器之间，以串联串行寄存器;以及一致检测电路，用于检测输出的数据的一致 从布置在由开关连接的串行寄存器的最后一端的最终串行寄存器与从紧接在最后串行寄存器之前排列的串行寄存器输出的数据组成。

    Memory device with page select capability
    214.
    发明授权
    Memory device with page select capability 失效
    带页面选择功能的内存设备

    公开(公告)号：US5485428A

    公开(公告)日：1996-01-16

    申请号：US248520

    申请日：1994-05-24

    Applicant: James J. Y. Lin

    Inventor： James J. Y. Lin

    IPC: G06F12/06 ,  G11C7/10 ,  G11C8/04 ,  G11C7/00

    CPC classification number: G11C7/1021 ,  G11C7/1018 ,  G11C7/1036 ,  G11C8/04

    Abstract: The invention provides a memory device having page select capability. The serial access memory device provided includes a first data terminal and a memory cell array having a plurality of address locations. The serial access memory device includes a shift register, an address decode circuit and a page select device. The page select device, in response to the access control signal, the address clock signal and the clock signal, selectively stores a page number therein.

    Abstract translation: 本发明提供一种具有页选择能力的存储装置。 提供的串行存取存储器件包括具有多个地址位置的第一数据端和存储单元阵列。 串行存取存储器件包括移位寄存器，地址解码电路和页选择器件。 页面选择装置响应于访问控制信号，地址时钟信号和时钟信号，在其中选择性地存储页码。

    MEMORY DEVICE AND METHOD FOR CONTROLLING ROW HAMMER
    215.
    发明公开
    MEMORY DEVICE AND METHOD FOR CONTROLLING ROW HAMMER 审中-公开

    公开(公告)号：US20240221815A1

    公开(公告)日：2024-07-04

    申请号：US18607520

    申请日：2024-03-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ho-Youn KIM

    IPC: G11C11/406 ,  G11C7/10

    CPC classification number: G11C11/40615 ,  G11C7/1036 ,  G11C11/40622

    Abstract: A row hammer control method and a memory device are provided. The memory device monitors the row hammer address(es) having the number of accesses equal to or more than a predetermined number of times or having a higher number of accesses as compared with other access addresses during the first row hammer monitoring time frame and malicious row hammer address(es) accessed at random sampling time points during the second row hammer monitoring time frame and being the same as the row hammer address(es), notifies a memory controller of the malicious row hammer address(es) when the number of malicious row hammer addresses exceeds a threshold value, and causes a target refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address(es) to be performed.

    Method for synchronising analogue data at the output of a plurality of digital/analogue converters
    216.
    发明授权
    Method for synchronising analogue data at the output of a plurality of digital/analogue converters 有权

    公开(公告)号：US12009833B2

    公开(公告)日：2024-06-11

    申请号：US17636820

    申请日：2020-08-19

    Applicant: Teledyne e2v Semiconductors SAS

    Inventor： Quentin Béraud-Sudreau ,  Jérôme Ligozat ,  Rémi Laube ,  Marc Stackler

    IPC: H03M7/00 ,  G11C7/10 ,  H03K19/17736 ,  H03M1/12

    CPC classification number: H03M1/1255 ,  G11C7/1036 ,  H03K19/1774 ,  H03M1/1215

    Abstract: A method for synchronizing analog data (Data_ana1, Data_ana2) at the output of a plurality of digital/analog converters (DAC), comprising at least one conversion core (C1, C2), on an active edge of a common reference clock (Clk), the method comprising the following steps: a) supplying an external synchronization signal (SYNC_ext), to at least one converter, and supplying a signal of the common reference clock to the plurality of converters; b) generating, within each converter, an internal synchronization signal (SYNC_int), such that all the internal synchronization signals are aligned on an active edge of the common reference clock; c) for each of the converters, generating a start signal (START1, START2) which represents the start of the sending of digital data and counting a number of clock strokes until the internal synchronization signal is generated, and; d) applying a delay Ri (R1, R2) to each converter core, the delay being equal to the difference between the highest number counted in step c) and the number counted for the core. Device for implementing such a method.

    Circuits and methods for in-memory computing
    219.
    发明授权
    Circuits and methods for in-memory computing 有权

    公开(公告)号：US11783875B2

    公开(公告)日：2023-10-10

    申请号：US17828964

    申请日：2022-05-31

    Applicant: The Trustees of Columbia University in the City of New York

    Inventor： Mingoo Seok ,  Zhewei Jiang ,  Jae-sun Seo ,  Shihui Yin

    IPC: G11C7/10 ,  G11C15/04 ,  G06F7/501 ,  G06F7/544 ,  G11C16/34

    CPC classification number: G11C7/1036 ,  G06F7/501 ,  G06F7/5443 ,  G11C7/1051 ,  G11C7/1078 ,  G11C15/04 ,  G11C15/043 ,  G11C16/3404

    Abstract: In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments. With one analog-to-digital converter (ADC) per column, the macro cab realize fully parallel vector-matrix multiplication in a single cycle in accordance with some embodiments.

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