公开(公告)号：US5659951A

公开(公告)日：1997-08-26

申请号：US632232

申请日：1996-04-15

Applicant: Thomas Patrick Gall ,  David Brian Stone ,  Russell Thomas White, Jr. ,  James Robert Wilcox

Inventor： Thomas Patrick Gall ,  David Brian Stone ,  Russell Thomas White, Jr. ,  James Robert Wilcox

IPC: H05K1/11 ,  H05K1/14 ,  H05K3/18 ,  H05K3/42 ,  H05K3/36

CPC classification number: H05K1/116 ,  H05K1/144 ,  H05K3/426 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K3/181 ,  H05K3/429 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A method for making a printed circuit board with a flush surface land begins by forming a multi-layer printed circuit board with a recess in a surface dielectric layer. Then, a hole is drilled into or through the printed circuit board; the hole communicates with the recess. After the recess is formed, a conductive material is provided in the recess to form a surface land and provided on an inner surface of the hole to form a plated hole which is electrically connected to the surface land. The conductive material in the recess has a thickness substantially equal to a depth of the recess such that the surface land is flush with an adjacent surface of the dielectric surface layer.

Abstract translation: 通过在表面电介质层中形成具有凹部的多层印刷电路板，来制造具有平坦表面的印刷电路板的方法。 然后，在印刷电路板中穿过或穿过孔; 孔与凹部连通。 在形成凹部之后，在凹部中设置导电材料以形成表面焊盘并且设置在孔的内表面上以形成电连接到表面焊盘的电镀孔。 凹部中的导电材料的厚度基本上等于凹部的深度，使得表面焊盘与电介质表面层的相邻表面齐平。

公开(公告)号：US5514449A

公开(公告)日：1996-05-07

申请号：US803087

申请日：1991-12-05

Applicant: Jeanne M. Tingerthal ,  Gregory P. Dado

Inventor： Jeanne M. Tingerthal ,  Gregory P. Dado

IPC: B32B27/08 ,  H01L21/48 ,  H01L23/14 ,  H05K3/24 ,  H05K3/46 ,  B32B3/00

CPC classification number: B32B27/08 ,  H01L21/4857 ,  H01L23/145 ,  H05K3/4647 ,  H01L2924/0002 ,  H05K2201/0129 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2203/068 ,  H05K2203/0733 ,  H05K3/243 ,  Y10S428/901 ,  Y10T428/24802 ,  Y10T428/24917 ,  Y10T428/31504 ,  Y10T428/31533 ,  Y10T428/31623 ,  Y10T428/31678 ,  Y10T428/31681 ,  Y10T428/31692 ,  Y10T428/31721

Abstract: An interconnect substrate comprising a metal-polymer composite incorporating microelectronic circuitry, which interconnect substrate is characterized by the feature that the polymer comprises alternating layers of thermoset and thermoplastic resins, said thermoplastic resins being resistant to the highest temperature to which the interconnect substrate may be heated, said thermoset resins being selected from the group consisting of bismaleimides, thermosetting polyimides, benzocyclobutenes and cyanate esters, said thermoplastic resin being selected from the group consisting of preimidized polyetherimides, and polyesters including polyacrylates, polyamides, polyvinylacetals, and phenoxy resins, said substrate having a durable base.

Abstract translation: 包含结合微电子电路的金属 - 聚合物复合物的互连基底，其互连基底的特征在于该聚合物包含交替的热固性树脂和热塑性树脂层，所述热塑性树脂耐受互连基底可被加热的最高温度 所述热固性树脂选自双马来酰亚胺，热固性聚酰亚胺，苯并环丁烯和氰酸酯，所述热塑性树脂选自预聚醚酰亚胺和聚酯，包括聚丙烯酸酯，聚酰胺，聚乙烯醇缩乙醛和苯氧树脂，所述基材具有 一个耐用的基地。

公开(公告)号：US5382315A

公开(公告)日：1995-01-17

申请号：US120264

申请日：1993-09-13

Applicant: Nalin Kumar

Inventor： Nalin Kumar

IPC: H01J9/02 ,  H01L21/48 ,  H01L21/60 ,  H01L23/485 ,  H05K1/14 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/14 ,  H05K3/18 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/465 ,  H01J9/025 ,  H01L21/4857 ,  H01L24/11 ,  H01L24/13 ,  H05K3/045 ,  H05K3/184 ,  H01J2201/30407 ,  H01J2201/30457 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/19041 ,  H05K1/142 ,  H05K2201/0154 ,  H05K2201/0166 ,  H05K2201/0376 ,  H05K2201/2081 ,  H05K2203/0554 ,  H05K2203/107 ,  H05K2203/121 ,  H05K2203/1338 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/107 ,  H05K3/143 ,  H05K3/146 ,  H05K3/185 ,  H05K3/388 ,  H05K3/4644 ,  H05K3/4661 ,  Y10S438/942

Abstract: A method of forming an etch mask and patterning a substrate. The method includes directing a particle beam at a substrate without using a mask to deposit an etch mask on the substrate which selectively exposes predetermined portions of the substrate, the etch mask consisting of particles mechanically placed on the substrate by the particle beam, and then etching the exposed portions of the substrate through the etch mask to form channels therein. The process is well suited to fabricating high density copper/polyimide multi-chip modules.

Abstract translation: 一种形成蚀刻掩模和图案化衬底的方法。 该方法包括在基板上引导粒子束而不使用掩模在基板上沉积选择性地暴露基板的预定部分的蚀刻掩模，该蚀刻掩模由颗粒束机械地放置在基板上的颗粒组成，然后蚀刻 通过蚀刻掩模的衬底的暴露部分在其中形成通道。 该工艺非常适合制造高密度铜/聚酰亚胺多芯片模块。

公开(公告)号：US5354593A

公开(公告)日：1994-10-11

申请号：US973939

申请日：1992-11-10

Applicant: Paul E. Grandmont ,  Harold Lake ,  Richard A. Anderson

Inventor： Paul E. Grandmont ,  Harold Lake ,  Richard A. Anderson

IPC: H01L21/48 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18 ,  H05K3/24 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  B32B9/00

CPC classification number: H05K3/465 ,  H01L21/4857 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0554 ,  H05K2203/107 ,  H05K3/002 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/184 ,  H05K3/244 ,  H05K3/389 ,  H05K3/422 ,  H05K3/4661 ,  Y10S428/901 ,  Y10S428/913 ,  Y10T428/24322 ,  Y10T428/24917 ,  Y10T428/31678

Abstract: A microporous, photoprocessable, moderately hydrophilic material on which metal can be deposited directly using electroless plating techniques, and its use in preparing printed wiring boards and circuit components.

Abstract translation: 可以使用化学镀技术直接沉积金属的微孔，光可加工的中等亲水性材料，以及其用于制备印刷线路板和电路部件的用途。

公开(公告)号：US5308927A

公开(公告)日：1994-05-03

申请号：US77959

申请日：1993-06-18

Applicant: Norihiro Hosoi

Inventor： Norihiro Hosoi

IPC: H01L21/48 ,  H05K1/00 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K1/09

CPC classification number: H01L21/4857 ,  H05K3/105 ,  H05K3/108 ,  H05K3/24 ,  H05K1/0393 ,  H05K2201/0154 ,  H05K2201/0317 ,  H05K2201/0376 ,  H05K2201/2063 ,  H05K2203/092 ,  H05K2203/1136 ,  H05K3/064 ,  H05K3/107

Abstract: A wiring board, which can be efficiency produced and has excellent heat resistance, and a method of manufacturing the same. With ion-irradiation, a conductive layer and a metal layer are formed in an insulating substrate. In the vicinity of the interface between the insulating substrate and the metal layer, a composition region, which includes the atoms of the insulating substrate and the metal layer, is formed by applying ions to a metal layer formed in the insulating substrate.

Abstract translation: 可以有效率地制造并具有优异的耐热性的布线板及其制造方法。 通过离子照射，在绝缘基板中形成导电层和金属层。 在绝缘基板和金属层之间的界面附近，通过向形成在绝缘基板上的金属层施加离子而形成包含绝缘基板和金属层的原子的组成区域。

公开(公告)号：US5266446A

公开(公告)日：1993-11-30

申请号：US890331

申请日：1992-05-26

Applicant: Kenneth Chang ,  George Czornyj ,  Mukta S. Farooq ,  Ananda H. Kumar ,  Marvin S. Pitler ,  Heinz O. Steimel

Inventor： Kenneth Chang ,  George Czornyj ,  Mukta S. Farooq ,  Ananda H. Kumar ,  Marvin S. Pitler ,  Heinz O. Steimel

IPC: H01L21/48 ,  H01L21/768 ,  H05K3/00 ,  H05K3/18 ,  H05K3/38 ,  H05K3/46 ,  G03C5/00 ,  H01L21/283

CPC classification number: H01L21/76808 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/76807 ,  H05K3/465 ,  H05K3/467 ,  H01L2221/1031 ,  H01L2221/1036 ,  H05K2201/0154 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/107 ,  H05K3/0023 ,  H05K3/0041 ,  H05K3/184 ,  H05K3/388 ,  H05K3/4661

Abstract: A method of making a multilayer thin film structure on the surface of a dielectric substrate which includes the steps of:a. forming a multilayer thin film structure including the steps of:applying a first layer of dielectric polymeric material on the surface of a dielectric substrate,applying a second layer of dielectric polymeric material over the first layer of polymeric material wherein the second polymeric material is photosensitive,imagewise exposing and developing the second polymeric material to form a feature therein, the second layer feature in communication with at least one feature formed in the first polymeric material; andb. filling the features in the entire multilayer structure simultaneously with conductive material.Preferably, the first layer feature is a via and the second layer feature is a capture pad or wiring channel. Also disclosed is a multilayer thin film structure made by this method.

Abstract translation: 一种在电介质基片的表面上形成多层薄膜结构的方法，包括以下步骤：a。 形成多层薄膜结构，其包括以下步骤：将第一层电介质聚合材料施加在电介质基底的表面上，在第一聚合物材料层上施加第二层电介质聚合材料，其中第二聚合物材料是光敏的， 成像曝光和显影第二聚合物材料以在其中形成特征，第二层特征与形成在第一聚合物材料中的至少一个特征连通; 和b。 与导电材料同时填充整个多层结构中的特征。 优选地，第一层特征是通孔，第二层特征是捕获垫或布线通道。 还公开了通过该方法制造的多层薄膜结构。

公开(公告)号：US5260170A

公开(公告)日：1993-11-09

申请号：US461857

申请日：1990-01-08

Applicant: Vernon L. Brown

Inventor： Vernon L. Brown

IPC: G03F7/00 ,  H05K3/00 ,  H05K3/18 ,  H05K3/46 ,  G03C5/58

CPC classification number: H05K3/465 ,  G03F7/002 ,  G03F7/0035 ,  H05K3/4661 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2203/1157 ,  H05K2203/125 ,  H05K3/0023 ,  H05K3/184

Abstract: A dielectric layered sequentially processed circuit board is disclosed. A first photodefinable resin containing an electroless plating catalyst is disposed on a substrate and portions of the substrate are exposed through the first resin. A second photodefinable resin absent the electroless plating catalyst is disposed on the first resin, and portions coincident with the exposed portions of the substrate as well as portions of the first resin are exposed through the second resin. A conductive material is deposited on the exposed portions of the substrate and the exposed portions of the first resin.

Abstract translation: 公开了一种电介质层状顺序处理电路板。 含有化学镀催化剂的第一光可固化树脂设置在基材上，并且基板的部分通过第一树脂曝光。 没有化​​学镀催化剂的第二光可固化树脂设置在第一树脂上，并且与基板的暴露部分重合的部分以及第一树脂的部分通过第二树脂暴露。 导电材料沉积在基板的暴露部分和第一树脂的暴露部分上。

公开(公告)号：US5152868A

公开(公告)日：1992-10-06

申请号：US664342

申请日：1991-03-04

Applicant: Andre Schiltz ,  Marie-Jeanne Bouzid

Inventor： Andre Schiltz ,  Marie-Jeanne Bouzid

IPC: H01L21/60 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R11/01 ,  H05K3/00 ,  H05K3/02 ,  H05K3/04 ,  H05K3/10 ,  H05K3/14 ,  H05K3/16 ,  H05K3/46

CPC classification number: H05K3/107 ,  H01L21/4846 ,  H01L23/4985 ,  H01L23/5387 ,  H05K3/048 ,  H01L2924/0002 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K3/0041 ,  H05K3/146 ,  H05K3/16 ,  H05K3/467 ,  Y10S428/901 ,  Y10T29/49204 ,  Y10T428/24917

Abstract: An elastomer connector is disclosed for integrated circuits or similar, comprising an elastomer material support on one face of which is formed a dense network of electro-conducting lines. Using photo-etching techniques and metal deposition on a layer of strippable material, which techniques are used for manufacturing integrated circuits, the lines may be given a very small width and very high conductivity.

Abstract translation: 公开了用于集成电路或类似物的弹性体连接器，其包括弹性体材料支撑件，其一面上形成有致密网络的导电线。 使用光刻技术和金属沉积在可剥离材料层上，哪些技术用于制造集成电路，这些线可以被给予非常小的宽度和非常高的导电性。

公开(公告)号：US4722765A

公开(公告)日：1988-02-02

申请号：US946115

申请日：1986-12-23

Applicant: Peter Ambros ,  Walter Budig ,  Gisela Westermeir

Inventor： Peter Ambros ,  Walter Budig ,  Gisela Westermeir

IPC: H01C17/06 ,  H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K3/20 ,  H05K3/38 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC classification number: H01L24/96 ,  H05K1/167 ,  H05K3/207 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/181 ,  H01L2924/19043 ,  H05K1/036 ,  H05K1/095 ,  H05K2201/0376 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0315 ,  H05K3/386 ,  Y10T29/49155 ,  Y10T428/12396 ,  Y10T428/12611 ,  Y10T428/12903

Abstract: The present invention describes an improved reverse lamination process forreparing printed circuits with resistors, conductor strips and/or contacts integrated in the circuit. A separating layer is applied on a metallic intermediate carrier. The intermediate carrier thus coated is then printed with a conductive paste in a desired. mirror-inverted layout to provide the resistors, conductor strips and/or contacts. This is followed by the lamination which is carried out under temperature effect and under pressure, the thus laminated package comprising the intermediate carrier, an intermediate layer and the final substrate. The intermediate carrier is subsequently removed, and the separating layer is etched off. The separating layer acts as a parting agent to permit easy mechanical separation and reuse of the metallic intermediate carrier.

Abstract translation: 本发明描述了一种用于制备具有集成在电路中的电阻器，导体条和/或触点的印刷电路的改进的反向叠层工艺。 将分离层施加在金属中间载体上。 然后将如此涂覆的中间载体以所需的方式印刷导电浆料。 镜面反向布局以提供电阻器，导体条和/或触点。 之后是在温度效应和压力下进行的层压，这样层压的包装包括中间载体，中间层和最终的基材。 随后除去中间载体，并剥离分离层。 分离层用作分离剂，以允许金属中间体载体的容易的机械分离和再利用。

公开(公告)号：US4705606A

公开(公告)日：1987-11-10

申请号：US697092

申请日：1985-01-31

Applicant: Peter L. Young ,  Jay Cech ,  Kin Li

Inventor： Peter L. Young ,  Jay Cech ,  Kin Li

IPC: H01L21/3205 ,  H01L21/48 ,  H01L23/14 ,  H01L23/538 ,  H05K1/00 ,  H05K3/00 ,  H05K3/10 ,  H05K3/24 ,  H05K3/38 ,  H05K3/46 ,  C25D5/02

CPC classification number: H01L23/147 ,  H01L21/4846 ,  H01L23/538 ,  H05K3/107 ,  H05K3/465 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L24/73 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K1/0289 ,  H05K2201/0154 ,  H05K2201/0376 ,  H05K2203/0723 ,  H05K2203/0733 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/242 ,  H05K3/244 ,  H05K3/388 ,  H05K3/4644

Abstract: A method for fabricating thin-film multilayer interconnect signal planes for connecting semiconductor integrated circuits is described. In this method, a first pattern of thin-film metallic interconnect lines is formed on a surface of a substrate. Then a first dielectric layer is formed over the entire surface of the substrate covering the pattern of thin-film metallic interconnect lines. A portion of the dielectric layer is then removed to expose the thin-film metallic interconnect lines so that a series of trenches is formed above each interconnect line. The interconnect lines are then electroplated to form a series of thicker metal interconnect lines such that the thicker metal interconnect lines and the dielectric layer form a substantially planer surface. This process can then be repeated in its entirely to form a plurality of interconnect signal planes. In the preferred embodiment, metallic vias are provided between each layer of metallic interconnect lines for electrical connection purposes.

Abstract translation: 描述了用于连接半导体集成电路的制造薄膜多层互连信号面的方法。 在该方法中，在基板的表面上形成薄膜金属互连线的第一图案。 然后，在覆盖薄膜金属互连线图形的基板的整个表面上形成第一电介质层。 然后去除电介质层的一部分以暴露薄膜金属互连线，使得在每个互连线上方形成一系列沟槽。 然后将互连线电镀以形成一系列较厚的金属互连线，使得较厚的金属互连线和电介质层形成基本上平的表面。 然后可以将该过程完全重复以形成多个互连信号平面。 在优选实施例中，为了电连接目的，金属通孔设置在每层金属互连线之间。