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公开(公告)号：US20180295723A1
公开(公告)日：2018-10-11
申请号：US16008060
申请日：2018-06-14
Applicant: Unimicron Technology Corp.
Inventor： Ming-Hao Wu , Wen-Fang Liu
CPC classification number: H05K1/111 , H05K1/115 , H05K3/0044 , H05K3/3452 , H05K3/4697 , H05K2201/0376 , H05K2203/0228 , H05K2203/025
Abstract: A manufacturing method of a circuit board structure includes the following steps: providing an inner circuit structure which includes a core layer; performing a build-up process to laminate a first build-up circuit structure on a first patterned circuit layer of the inner circuit structure, wherein the first build-up circuit structure includes an inner dielectric layer, and the inner dielectric layer directly covers an upper surface of the core layer and the first patterned circuit layer; removing a portion of the first build-up circuit structure to form an opening extending from a first surface of the first build-up circuit structure relatively far away from the inner circuit structure to a portion of the inner dielectric layer; performing a sandblasting process on a first inner surface of the inner dielectric layer exposed by the opening to at least remove the portion of the inner dielectric layer exposed by the opening.
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公开(公告)号：US10039184B2
公开(公告)日：2018-07-31
申请号：US15427061
申请日：2017-02-08
Applicant: Unimicron Technology Corp.
Inventor： Ming-Hao Wu , Wen-Fang Liu
CPC classification number: H05K1/111 , H05K1/115 , H05K3/0044 , H05K3/3452 , H05K3/4697 , H05K2201/0376 , H05K2203/0228 , H05K2203/025
Abstract: A circuit board structure includes an inner circuit structure and a first build-up circuit structure. The inner circuit structure includes a core layer having an upper surface and a lower surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface and a conductive via connecting the first and the second patterned circuit layers. The first build-up circuit structure is disposed on the upper surface of the core layer and covers the first patterned circuit layer, wherein the first build-up circuit structure at least has a cavity, the cavity exposes a portion of the first patterned circuit layer and a cross-sectional profile of an edge of a top surface of the portion of the first patterned circuit layer exposed by the cavity is a curved surface.
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公开(公告)号：US10002825B2
公开(公告)日：2018-06-19
申请号：US15625083
申请日：2017-06-16
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Shih-Chao Chiu , Chun-Hsien Lin , Yu-Cheng Pai , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L23/498 , H05K1/18 , H01L23/538 , H05K3/00 , H01L21/683 , H05K3/32 , H05K3/10 , H01L23/00 , H05K1/02 , H05K3/46 , H01L23/31
CPC classification number: H01L23/49838 , H01L21/6835 , H01L23/3121 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2221/68318 , H01L2221/68345 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/16237 , H01L2224/26175 , H01L2224/2919 , H01L2224/32058 , H01L2224/32105 , H01L2224/32106 , H01L2224/32237 , H01L2224/73204 , H01L2224/81801 , H01L2224/83101 , H01L2924/15313 , H01L2924/18161 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104 , H05K1/0231 , H05K1/185 , H05K1/186 , H05K1/189 , H05K3/0026 , H05K3/007 , H05K3/108 , H05K3/32 , H05K3/4682 , H05K2201/0376 , H05K2201/10515 , H05K2201/1053 , H05K2201/10674 , H05K2201/10977 , H01L2924/014 , H01L2924/00014 , H01L2924/0665
Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
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公开(公告)号：US20180132349A1
公开(公告)日：2018-05-10
申请号：US15864754
申请日：2018-01-08
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
CPC classification number: H05K3/42 , H05K1/0284 , H05K1/0296 , H05K1/112 , H05K3/007 , H05K3/4647 , H05K2201/0376 , H05K2203/0733 , H05K2203/1476 , Y10T29/49165
Abstract: A manufacturing method of a double layer circuit board comprises forming at least one connecting pillar on a first circuit, wherein the at least one connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the at least one connecting pillar; drilling the substrate to expose a portion of the second end of the at least one connecting pillar, wherein the other portion of the second end of the at least one connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the at least one connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.
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5.发明授权公开(公告)号：US09936590B2
公开(公告)日：2018-04-03
申请号：US15626437
申请日：2017-06-19
Applicant: Second Sight Medical Products, Inc.
Inventor： Jerry Ok , Robert J Greenberg
IPC: C03B29/00 , B32B37/00 , B29C65/00 , H05K3/40 , H05K3/00 , H05K3/46 , C04B37/00 , H05K3/12 , B32B37/14 , H05K1/03
CPC classification number: H05K3/4061 , B32B37/14 , C04B35/10 , C04B37/00 , C04B2237/064 , H05K1/0306 , H05K3/0044 , H05K3/0047 , H05K3/005 , H05K3/12 , H05K3/1225 , H05K3/1233 , H05K3/4614 , H05K3/4623 , H05K3/4629 , H05K2201/0376 , H05K2201/096 , H05K2201/09609 , H05K2203/1147 , H05K2203/308 , Y10T156/10
Abstract: A method for fabricating a biocompatible hermetic housing including electrical feedthroughs, the method comprises providing a ceramic sheet having an upper surface and a lower surface, forming at least one via hole in said ceramic sheet extending from said upper surface to said lower surface, inserting a conductive thick film paste into said via hole, laminating the ceramic sheet with paste filled via hole between an upper ceramic sheet and a lower ceramic sheet to form a laminated ceramic substrate, firing the laminated ceramic substrate to a temperature to sinter the laminated ceramic substrate and cause the paste filled via hole to form metalized via and cause the laminated ceramic substrate to form a hermetic seal around said metalized via, and removing the upper ceramic sheet and the lower ceramic sheet material from the fired laminated ceramic substrate to expose an upper and a lower surface of the metalized via.
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Patent Agency Ranking
公开(公告)号：US09867286B2
公开(公告)日：2018-01-09
申请号：US14901008
申请日：2014-06-25
Inventor： Samantha Lichter , Nicholas Apollo , David Garrett , Kumaravelu Ganesan , Hamish Meffin , Steven Prawer
IPC: A61N1/375 , H05K1/03 , H01L23/14 , H01L23/053 , H05K1/09 , H05K3/10 , A61N1/36 , H05K1/11 , H05K3/00 , H05K3/14 , A61N1/05
CPC classification number: H05K1/0306 , A61N1/0543 , A61N1/36046 , H01L23/053 , H01L23/14 , H01L2224/14 , H01L2224/17 , H01L2924/0002 , H05K1/09 , H05K1/111 , H05K3/0044 , H05K3/107 , H05K3/146 , H05K2201/0323 , H05K2201/0376 , H01L2924/00
Abstract: A circuit board is described. The circuit board comprises an electrically insulating diamond material having a surface. The electrically insulating diamond material has at least one recess extending into only a portion of a thickness of the electrically insulating diamond material from the surface of the electrically insulating diamond material. The circuit board also comprises an electrically conductive material located at least partially within the recess.
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公开(公告)号：US20170352615A1
公开(公告)日：2017-12-07
申请号：US15625083
申请日：2017-06-16
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Shih-Chao Chiu , Chun-Hsien Lin , Yu-Cheng Pai , Wei-Chung Hsiao , Ming-Chen Sun , Tzu-Chieh Shen , Chia-Cheng Chen
IPC: H01L23/498 , H01L23/538 , H05K3/32 , H05K3/00 , H05K1/18 , H01L21/683 , H05K3/46 , H01L23/00 , H01L23/31 , H05K1/02 , H05K3/10
CPC classification number: H01L23/49838 , H01L21/6835 , H01L23/3121 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2221/68318 , H01L2221/68345 , H01L2224/131 , H01L2224/13147 , H01L2224/16227 , H01L2224/16237 , H01L2224/26175 , H01L2224/2919 , H01L2224/32058 , H01L2224/32105 , H01L2224/32106 , H01L2224/32237 , H01L2224/73204 , H01L2224/81801 , H01L2224/83101 , H01L2924/15313 , H01L2924/18161 , H01L2924/19041 , H01L2924/19103 , H01L2924/19104 , H05K1/0231 , H05K1/185 , H05K1/186 , H05K1/189 , H05K3/0026 , H05K3/007 , H05K3/108 , H05K3/32 , H05K3/4682 , H05K2201/0376 , H05K2201/10515 , H05K2201/1053 , H05K2201/10674 , H05K2201/10977 , H01L2924/014 , H01L2924/00014 , H01L2924/0665
Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.
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公开(公告)号：US09839124B2
公开(公告)日：2017-12-05
申请号：US15015551
申请日：2016-02-04
Applicant: JX NIPPON MINING & METALS CORPORATION
Inventor： Michiya Kohiki
IPC: H05K1/09 , H05K3/00 , C25D1/04 , H05K3/20 , C25D7/06 , H05K3/02 , H05K3/40 , H05K3/42 , C25D3/04 , C25D3/18 , C25D3/38 , C25D3/56 , C25D5/14 , C23C18/16
CPC classification number: H05K1/09 , C23C18/1653 , C25D1/04 , C25D3/04 , C25D3/18 , C25D3/38 , C25D3/562 , C25D5/14 , C25D7/0614 , H05K3/0058 , H05K3/025 , H05K3/205 , H05K3/4007 , H05K3/421 , H05K2201/0355 , H05K2201/0367 , H05K2201/0376 , H05K2201/09509 , H05K2203/0152 , H05K2203/0156 , H05K2203/0307 , H05K2203/0723 , H05K2203/0726
Abstract: Provided is a copper foil provided with a carrier in which the laser hole-opening properties of the ultrathin copper layer are good and which is suitable for producing a high-density integrated circuit substrate. A copper foil provided with a carrier having, in order, a carrier, an intermediate layer, and an ultrathin copper layer, wherein the specular gloss at 60° in an MD direction of the intermediate layer side surface of the ultrathin copper layer is 140 or less.
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公开(公告)号：US09812412B2
公开(公告)日：2017-11-07
申请号：US14980404
申请日：2015-12-28
Applicant: ROHM CO., LTD.
Inventor： Takuma Shimoichi , Yasuhiro Kondo
CPC classification number: H01L23/66 , H01L27/016 , H01L28/10 , H01L28/20 , H01L28/60 , H01L2223/6672 , H01L2924/0002 , H05K1/0289 , H05K1/029 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/107 , H05K3/146 , H05K2201/0317 , H05K2201/0338 , H05K2201/0376 , H05K2201/0391 , H05K2201/09263 , H05K2201/09981 , H05K2201/10181 , H05K2203/0353 , H05K2203/1338 , H01L2924/00
Abstract: A chip part includes a substrate, a first electrode and a second electrode which are formed apart from each other on the substrate and a circuit network which is formed between the first electrode and the second electrode. The circuit network includes a first passive element including a first conductive member embedded in a first trench formed in the substrate and a second passive element including a second conductive member formed on the substrate outside the first trench.
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10.发明申请公开(公告)号：US20170290171A1
公开(公告)日：2017-10-05
申请号：US15626437
申请日：2017-06-19
Applicant: Second Sight Medical Products, Inc.
Inventor： Jerry Ok , Robert J. Greenberg
CPC classification number: H05K3/4061 , B32B37/14 , C04B35/10 , C04B37/00 , C04B2237/064 , H05K1/0306 , H05K3/0044 , H05K3/0047 , H05K3/005 , H05K3/12 , H05K3/1225 , H05K3/1233 , H05K3/4614 , H05K3/4623 , H05K3/4629 , H05K2201/0376 , H05K2201/096 , H05K2201/09609 , H05K2203/1147 , H05K2203/308 , Y10T156/10
Abstract: A method for fabricating a biocompatible hermetic housing including electrical feedthroughs, the method comprises providing a ceramic sheet having an upper surface and a lower surface, forming at least one via hole in said ceramic sheet extending from said upper surface to said lower surface, inserting a conductive thick film paste into said via hole, laminating the ceramic sheet with paste filled via hole between an upper ceramic sheet and a lower ceramic sheet to form a laminated ceramic substrate, firing the laminated ceramic substrate to a temperature to sinter the laminated ceramic substrate and cause the paste filled via hole to form metalized via and cause the laminated ceramic substrate to form a hermetic seal around said metalized via, and removing the upper ceramic sheet and the lower ceramic sheet material from the fired laminated ceramic substrate to expose an upper and a lower surface of the metalized via.
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