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    Flexible board
    215.
    发明授权
    Flexible board 有权
    弹性板

    公开(公告)号：US06346298B1

    公开(公告)日：2002-02-12

    申请号：US09456440

    申请日：1999-12-08

    Applicant: Satoshi Takahashi ,  Hidetsugu Namiki

    Inventor： Satoshi Takahashi ,  Hidetsugu Namiki

    IPC: B05D138

    CPC classification number: H05K1/0346 ,  H05K1/036 ,  H05K2201/0154 ,  H05K2201/068 ,  Y10T428/31681 ,  Y10T428/31721

    Abstract: A flexible board comprises metal foil 1 and provided thereon a laminated polyimide-based resin layer 2 of a three-layer structure comprising a first polyimide-based resin layer 2a, a second polyimide-based resin layer 2b, and a third polyimide-based resin layer 2c, wherein the following equation is satisfied. k1>k3>k2, where k1 is the coefficient of linear thermal expansion of the first polyimide-based resin layer 2a on the side of the metal foil 1, k2 is the coefficient of linear thermal expansion of the second polyimide-based resin layer 2b, and k3 is the coefficient of linear thermal expansion of the third polyimide-based resin layer 2c.

    Abstract translation: 柔性基板包括金属箔1，并且在其上设置三层结构的叠层的聚酰亚胺基树脂层2，其包括第一聚酰亚胺基树脂层2a，第二聚酰亚胺基树脂层2b和第三聚酰亚胺基树脂 层2c，其中满足以下等式。其中k1是第一聚酰亚胺类树脂层2a在金属箔1一侧的线性热膨胀系数，k2是第二聚酰亚胺树脂层2a的线性热膨胀系数， 并且k3是第三聚酰亚胺系树脂层2c的线热膨胀系数。

    Isolated flip chip or BGA to minimize interconnect stress due to thermal mismatch
    216.
    发明申请
    Isolated flip chip or BGA to minimize interconnect stress due to thermal mismatch 有权
    隔离倒装芯片或BGA，以尽量减少由于热失配引起的互连应力

    公开(公告)号：US20020011353A1

    公开(公告)日：2002-01-31

    申请号：US09960164

    申请日：2001-09-20

    Inventor： Sundar Kamath ,  David Chazan ,  Jan I. Strandberg ,  Solomon I. Beilin

    IPC: H05K001/03

    CPC classification number: H05K1/0271 ,  H01L23/3735 ,  H01L23/5383 ,  H01L2224/16225 ,  H01L2924/00014 ,  H05K1/0272 ,  H05K2201/0133 ,  H05K2201/068 ,  H05K2201/09109 ,  H05K2201/10416 ,  H05K2201/10734 ,  H01L2224/0401

    Abstract: A wiring substrate with reduced thermal expansion stress. A wiring substrate, such as a laminated PWB, thin film circuit, lead frame, or chip carrier accepts an integrated circuit, such as a die, a flip chip, or ball grid array package. The wiring substrate has a thermal expansion stress reduction insert, void, or constructive void in a thermal expansion stress region proximate to the integrated circuit. The thermal expansion stress reduction insert or void may extend a selected distance from the edge or edges of the integrated circuit attachment area. The thermal expansion stress reduction insert or void improves the flexibility of the wiring substrate in the region that is joined to the integrated circuit, thus reducing thermal stress between components of the wiring substrate-integrated circuit assembly. In another embodiment, layers of a laminated wiring substrate are intentionally not bonded beneath the chip attach area, thus allowing greater flexibility of the upper layer of the laminate.

    Abstract translation: 具有降低的热膨胀应力的布线基板。 诸如层叠PWB，薄膜电路，引线框架或芯片载体的布线基板可以接受诸如管芯，倒装芯片或球栅阵列封装的集成电路。 布线基板在靠近集成电路的热膨胀应力区域中具有热膨胀应力减小插入件，空隙或构造空隙。 热膨胀应力减小插入物或空隙可以从集成电路连接区域的边缘或边缘延伸选定的距离。 热膨胀应力减小插入物或空隙提高了接合到集成电路的区域中的布线基板的柔性，从而降低了布线基板集成电路组件的部件之间的热应力。 在另一个实施例中，层叠布线基板的层有意地不粘合在芯片附着区域下方，从而允许层压体的上层更大的灵活性。

    Power module substrate
    218.
    发明授权
    Power module substrate 有权
    电源模块基板

    公开(公告)号：US06310775B1

    公开(公告)日：2001-10-30

    申请号：US09531489

    申请日：2000-03-20

    Applicant: Yoshiyuki Nagatomo ,  Toshiyuki Nagase ,  Kazuaki Kubo ,  Shoichi Shimamura

    Inventor： Yoshiyuki Nagatomo ,  Toshiyuki Nagase ,  Kazuaki Kubo ,  Shoichi Shimamura

    IPC: H05K720

    CPC classification number: H05K1/0271 ,  C04B2237/407 ,  H01L23/3735 ,  H01L2224/32225 ,  H05K1/0306 ,  H05K3/0061 ,  H05K2201/0355 ,  H05K2201/068 ,  Y10S428/901

    Abstract: The present invention for solving the problem of suppressing the load caused by heat stress applied on an insulation substrate, reducing the manufacturing coat of a power module substrate, and improving productivity provides a power module substrate in which a buffer layer having a surface area one to three times as large as the surface area of the insulation substrate is laminated and bonded between the insulation substrate and the heat sink, wherein the buffer layer is formed using a material having a thermal expansion coefficient between the thermal expansion coefficients of the insulation substrate and the heat sink, the insulation substrate being preferably formed using AlN, Si3N4 or Al2O3, the buffer layer being preferably formed using AlSiC, and a carbon plate or a composite material of AlC, besides the thickness of the buffer layer being preferably 1.5 to 50 times as large as the thickness of the insulation substrate, and the insulation substrate, the buffer layer and the heat sink being preferably laminated via a brazing foil by bonding.

    Abstract translation: 本发明解决了由施加在绝缘基板上的热应力引起的负载的抑制问题，降低功率模块基板的制造涂层以及提高生产率的本发明提供了一种功率模块用基板，其中，缓冲层的表面积为1〜 将绝缘基板的表面积的3倍层叠并结合在绝缘基板和散热片之间，其中缓冲层使用具有绝热基板的热膨胀系数和 散热器，优选使用AlN，Si 3 N 4或Al 2 O 3形成绝缘基板，缓冲层优选使用AlSiC形成，并且碳板或AlC的复合材料除了缓冲层的厚度之外优选为1.5〜50倍 绝缘基板的厚度大，绝缘基板，缓冲层和热量大 水槽优选通过粘合通过钎焊箔层压。

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