Remapping of memory in memory control architectures

    公开(公告)号:US09823984B2

    公开(公告)日:2017-11-21

    申请号:US14749883

    申请日:2015-06-25

    Inventor: Leong Hock Sim

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for remapping of memory in memory control architectures. A processing device includes a processing core and a platform controller hub (PCH) coupled to the processing core. The PCH is to receive an indication of a failure associated with a first memory region of a plurality of memory regions residing in a memory. The PCH is also to interrupt an operating system to prompt for a reboot. Upon the reboot, the PCH is to remap a memory address range associated with the first memory region to a second memory region of the plurality of regions.

    Access point controller failover system

    公开(公告)号:US09798633B2

    公开(公告)日:2017-10-24

    申请号:US14557523

    申请日:2014-12-02

    CPC classification number: G06F11/2005 G06F11/1425 G06F2201/85 H04L69/40

    Abstract: An access point IHS group controller failover system includes a first access point IHS group controller that controls a first access point IHS group that includes plurality of access point IHSs. Following a failure of the first access point IHS group controller, the first access point IHS broadcasts a first access point IHS identifier to a first subset of the plurality of access point IHSs. The first access point IHS then registers the first subset of the plurality of access point IHSs as members of a second access point IHS group, and controls at least some functions of the second access point IHS group. When the first access point IHS detects activity from the first access point IHS group controller, it instructs the first subset of the plurality of access point IHSs in the second access point IHS group to reconnect to the first access point IHS group controller.

    Power failure detection system and method

    公开(公告)号:US09778988B2

    公开(公告)日:2017-10-03

    申请号:US14931824

    申请日:2015-11-03

    Abstract: A power failure monitoring system and a method are disclosed herein, where the power failure monitoring system includes a motherboard, a board, a complex programmable logic device (CPLD) and a baseboard management controller (BMC) module. The motherboard includes a central processing unit (CPU) power and a non-CPU power. The board includes a board power. The BMC module includes a register that is electrically coupled to the CPLD. The CPLD is configured to execute a shutdown process when power failure occurs, identify a power failure type, and determine whether to execute a restart process according to the power failure type. If the restart process is executed and a count of the restart process reaches a predetermined count, the CPLD records lock information in the register. The BMC module is configured to record the count of the restart process, and execute a lock process according to the lock information.

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