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231.发明授权公开(公告)号：US09742613B2
公开(公告)日：2017-08-22
申请号：US14937500
申请日：2015-11-10
Applicant: Maxlinear, Inc.
Inventor： Yongtao Wang , Curtis Ling , Timothy Gallagher
IPC: H03D3/22 , G01S3/16 , H04L27/38 , H04L27/36 , H04L27/233
CPC classification number: H04L27/3863 , H04L27/2334 , H04L27/2338 , H04L27/361 , H04L27/366
Abstract: Methods and systems for I/O mismatch calibration and compensation for wideband communication receivers may include receiving a radio frequency (RF) signal in a receiver of a communication device, down-sampling said received RF signal to generate a channel k and its image channel −k at baseband frequencies, determining average in-phase (I) and quadrature (Q) gain and phase mismatch of said channel k and said image channel −k, removing said average I and Q gain and phase mismatch of said channel k and said image channel −k, determining, after said removing said average I and Q gain and phase mismatch, a residual phase tilt of said channel k and said image channel −k, and compensating for said determined residual phase tilt of said channel k and said image channel −k utilizing a phase tilt correction filter.
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公开(公告)号：US09712886B2
公开(公告)日：2017-07-18
申请号：US15264060
申请日：2016-09-13
Applicant: MaxLinear, Inc.
Inventor： Madhukar Reddy , Timothy Gallagher
CPC classification number: H04N21/6118 , H04L12/2801 , H04N21/4385 , H04N21/6168
Abstract: Aspects of a method and apparatus for band separation for multiband communication systems are provided. One or more circuits for use in a transceiver may comprise a triplexer and a leakage processing module. The triplexer may comprise a first port, a Multimedia Over Coaxial Alliance (MoCA) port, a television upstream port, and a television downstream port. The leakage processing module may comprise a television downstream input port, a cable television downstream output port, a MoCA port, and a cable television upstream port. The leakage processing module may be operable to (1) process a MoCA signal to generate a first compensation signal; (2) process a cable upstream signal to generate a second compensation signal; (3) process a filtered signal based at least in part on the first and second compensation signals; and (4) output the processed filtered signal via the cable television downstream output port of said leakage processing module.
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公开(公告)号：US20170077953A1
公开(公告)日：2017-03-16
申请号：US15358473
申请日：2016-11-22
Applicant: MaxLinear, Inc.
Inventor： Mingrui Zhu , Curtis Ling , Timothy Gallagher
CPC classification number: H03M13/1114 , H03M13/1111 , H03M13/1125 , H03M13/1128 , H03M13/1131 , H03M13/1137 , H03M13/114 , H03M13/1165 , H03M13/616 , H03M13/6505 , H04L1/0045
Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.
Abstract translation: 在本公开的示例实现中，在低位奇偶校验（LDPC）解码器的消息传送期间，在第一比特组解码期间，可以在第一可变节点达到确定阈值的比特值概率时锁定第一可变节点 并且在连接到第一校验节点被锁定的所有变量节点上锁定第一校验节点。 所述LDPC解码器可以在所述LDPC解码器的所有可变节点被锁定，所述LDPC解码器的所有校验节点被锁定，达到最大迭代次数或达到超时之后，停止解码所述第一组位。 在第一可变节点被锁定的第一组比特的解码的特定迭代期间，LDPC解码器可以避免为锁定的第一可变节点生成比特值概率。
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公开(公告)号：US20170054491A1
公开(公告)日：2017-02-23
申请号：US15238877
申请日：2016-08-17
Applicant: Maxlinear, Inc.
Inventor： Timothy Gallagher , Curtis Ling
Abstract: Aspects of methods and systems for transceiver array synchronization are provided. An array based communications system comprises a plurality of transceiver circuits and an array coordinator. Each transceiver circuit of the plurality of transceiver circuits comprises a plurality of wireless transmitters and a local oscillator generator. Each wireless transmitter of the plurality of wireless transmitters is able to modulate a local oscillator signal from the local oscillator generator based on a weighted sum of a plurality of digital datastreams. The array coordinator is able to adjust a phase of a first local oscillator signal based on a phase difference between the first local oscillator signal and a second local oscillator signal. The first local oscillator signal is generated by a first local oscillator generator of a first transceiver circuit. The second local oscillator signal is generated by a second local oscillator generator of a second transceiver circuit.
Abstract translation: 提供了收发器阵列同步的方法和系统的方面。 基于阵列的通信系统包括多个收发器电路和阵列协调器。 多个收发器电路的每个收发器电路包括多个无线发射器和本地振荡器发生器。 多个无线发射机的每个无线发射机能够基于多个数字数据流的加权和来调制来自本地振荡器发生器的本地振荡器信号。 阵列协调器能够基于第一本地振荡器信号和第二本地振荡器信号之间的相位差来调整第一本地振荡器信号的相位。 第一本地振荡器信号由第一收发器电路的第一本地振荡器产生器产生。 第二本地振荡器信号由第二收发器电路的第二本地振荡器产生器产生。
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公开(公告)号：US20170054210A1
公开(公告)日：2017-02-23
申请号：US15238808
申请日：2016-08-17
Applicant: Maxlinear, Inc.
Inventor： Timothy Gallagher , Curtis Ling
CPC classification number: H01Q3/2611 , H04B7/18513
Abstract: An array based communications system may comprise a plurality of element processors. Each element processor may comprise a desired beam generation circuit and a suppression beam generation circuit. The desired beam generation circuit may generate a first plurality of complex coefficients. A desired beam may be generated according to a first weighted sum comprising a plurality of digital datastreams weighted by a corresponding complex coefficient of the first plurality of complex coefficients. The suppression beam generation circuit may generate a second plurality of complex coefficients. A suppression beam may be generated according to a second weighted sum comprising the plurality of digital datastreams weighted by a corresponding complex coefficient of the second plurality of complex coefficients.
Abstract translation: 基于阵列的通信系统可以包括多个元件处理器。 每个元件处理器可以包括期望的光束产生电路和抑制光束产生电路。 期望的波束产生电路可以产生第一多个复系数。 可以根据包括由第一多个复系数的相应复系数加权的多个数字数据流的第一加权和生成期望的波束。 抑制波束产生电路可以产生第二多个复系数。 可以根据包括由第二多个复系数的对应复系数加权的多个数字数据流的第二加权和来生成抑制波束。
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Patent Agency Ranking
236.发明申请Time and Frequency Allocation for Concurrent Communications on a Shared Coaxial Cable 审中-公开共享同轴电缆并发通信的时间和频率分配公开(公告)号：US20170012894A1
公开(公告)日：2017-01-12
申请号：US15205962
申请日：2016-07-08
Applicant: Maxlinear, Inc.
Inventor： Sridhar Ramesh , Curtis Ling , Timothy Gallagher
IPC: H04L12/911 , H04B17/309
CPC classification number: H04L47/72 , H04L47/822 , H04W52/367
Abstract: Circuitry for use in a network controller comprises a processor and memory. The network controller is operable to control communications in a network comprising a plurality of devices connected via a shared coaxial cable. The circuitry is operable to maintain one or more data structures that hold per-sender-receiver-pair link parameters and per-sender-receiver-pair bandwidth grant status. The circuitry is operable to, in response to receipt of a reservation request on the shared coaxial cable, decide which one or more of a plurality of subbands and which one or more of a plurality timeslots to reserve for the transmission based, at least in part, on the per-sender-receiver-pair link parameters and the per-sender-receiver-pair bandwidth grant status in the one or more data structures. The circuitry is operable to generate a reservation grant message that indicates the decided one or more subbands and the decided one or more timeslots.
Abstract translation: 用于网络控制器的电路包括处理器和存储器。 网络控制器可操作以控制包括通过共享同轴电缆连接的多个设备的网络中的通信。 该电路可操作以维护保持每发送器 - 接收器对链路参数和每发送器 - 接收器对带宽授权状态的一个或多个数据结构。 该电路可操作以响应于在共享同轴电缆上接收到预约请求，决定至少部分地基于多个子带中的哪一个或多个以及多个时隙中的哪一个或多个来为传输保留 ，在每个发送者 - 接收者对链路参数和一个或多个数据结构中的每发送者 - 接收者对带宽授权状态。 电路可操作以产生指示所确定的一个或多个子带和所确定的一个或多个时隙的预留许可消息。
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公开(公告)号：US09509422B2
公开(公告)日：2016-11-29
申请号：US14948436
申请日：2015-11-23
Applicant: MaxLinear, Inc.
Inventor： Glenn Chang , Raja Pullela , Madhukar Reddy , Timothy Gallagher , Shanta Murthy Prem Swaroop , Curtis Ling , Vamsi Paidi , Wenjian Chen
CPC classification number: H04H40/90 , H04N21/6143
Abstract: A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.
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公开(公告)号：US09509340B2
公开(公告)日：2016-11-29
申请号：US15075255
申请日：2016-03-21
Applicant: Maxlinear, Inc.
Inventor： Mingrui Zhu , Curtis Ling , Timothy Gallagher
CPC classification number: H03M13/1114 , H03M13/1111 , H03M13/1125 , H03M13/1128 , H03M13/1131 , H03M13/1137 , H03M13/114 , H03M13/1165 , H03M13/616 , H03M13/6505 , H04L1/0045
Abstract: In an example implementation of this disclosure, a message passing low density parity check (LDPC) decoder may, during decoding of a first group of bits, lock a first variable node upon a bit-value probability of the first variable node reaching a determined threshold, and lock a first check node upon all variable nodes connected to the first check node being locked. The LDPC decoder may cease decoding the first group of bits upon all variable nodes of the LDPC decoder being locked, all check nodes of the LDPC decoder being locked, reaching a maximum number of iterations, or reaching a timeout. During a particular iteration of the decoding of the first group of bits in which the first variable node is locked, the LDPC decoder may refrain from generating a bit-value probability for the locked first variable node.
Abstract translation: 在本公开的示例实现中，在低位奇偶校验（LDPC）解码器的消息传送期间，在第一比特组解码期间，可以在第一可变节点达到确定阈值的比特值概率时锁定第一可变节点 并且在连接到第一校验节点被锁定的所有变量节点上锁定第一校验节点。 所述LDPC解码器可以在所述LDPC解码器的所有可变节点被锁定，所述LDPC解码器的所有校验节点被锁定，达到最大迭代次数或达到超时之后，停止解码所述第一组位。 在第一可变节点被锁定的第一组比特的解码的特定迭代期间，LDPC解码器可以避免为锁定的第一可变节点生成比特值概率。
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公开(公告)号：US20160316276A1
公开(公告)日：2016-10-27
申请号：US15200109
申请日：2016-07-01
Applicant: MaxLinear, Inc.
Inventor： Curtis Ling , Timothy Gallagher , Sridhar Ramesh
IPC: H04N21/6587 , H04N7/10 , H04N21/6373 , H04N21/61 , H04N21/222 , H03M1/12 , H04H20/42
CPC classification number: H04N21/6587 , H03H17/0416 , H03M1/12 , H03M1/126 , H03M3/496 , H04H20/426 , H04H20/77 , H04H40/27 , H04J1/00 , H04N7/10 , H04N7/106 , H04N21/2221 , H04N21/6118 , H04N21/6373
Abstract: A network device may receive a signal from a headend, wherein a bandwidth of the received signal spans from a low frequency to a high frequency and encompasses a plurality of sub-bands. The network device may determine, based on communication with the headend, whether one of more of the sub-bands residing above a threshold frequency are available for carrying downstream data from the headend to the circuitry. The network device may digitize the signal using an ADC operating at a sampling frequency. The sampling frequency may be configured based on a result of the determining. When the sub-band(s) are available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively high frequency. When the sub-band(s) are not available for carrying downstream data from the headend to the network device, the sampling frequency may be set to a relatively low frequency.
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240.发明授权Method and apparatus for band separation for multiband communication systems 有权用于多频段通信系统的频带分离的方法和装置公开(公告)号：US09445149B2
公开(公告)日：2016-09-13
申请号：US14230058
申请日：2014-03-31
Applicant: MaxLinear, Inc.
Inventor： Madhukar Reddy , Timothy Gallagher
CPC classification number: H04N21/6118 , H04L12/2801 , H04N21/4385 , H04N21/6168
Abstract: Aspects of a method and apparatus for band separation for multiband communication systems are provided. One or more circuits for use in a transceiver may comprise a triplexer and a leakage processing module. The triplexer may comprise a multiband port, a Multimedia Over Coaxial Alliance (MoCA) port, a television upstream port, and a television downstream port. The leakage processing module may comprise a television downstream input port, a cable television downstream output port, a MoCA port, and a cable television upstream port. The leakage processing module may be operable to (1) process a MoCA signal to generate a first compensation signal; (2) process a cable upstream signal to generate a second compensation signal; (3) process a filtered signal based at least in part on the first and second compensation signals; and (4) output the processed filtered signal via the cable television downstream output port of said leakage processing module.
Abstract translation: 提供了用于多频带通信系统的频带分离的方法和装置的方面。 在收发器中使用的一个或多个电路可以包括三工器和泄漏处理模块。 三工器可以包括多频带端口，多媒体同轴联盟（MoCA）端口，电视上行端口和电视下行端口。 泄漏处理模块可以包括电视下游输入端口，有线电视下游输出端口，MoCA端口和有线电视上行端口。 泄漏处理模块可操作为（1）处理MoCA信号以产生第一补偿信号; （2）处理电缆上行信号以产生第二补偿信号; （3）至少部分地基于第一和第二补偿信号来处理滤波信号; 和（4）经由所述泄漏处理模块的有线电视下游输出端口输出经处理的滤波信号。
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