公开(公告)号：US07704765B2

公开(公告)日：2010-04-27

申请号：US11889110

申请日：2007-08-09

Applicant: Junya Maruyama ,  Atsuo Isobe ,  Susumu Okazaki ,  Koichiro Tanaka ,  Yoshiaki Yamamoto ,  Koji Dairiki ,  Tomoko Tamura

Inventor： Junya Maruyama ,  Atsuo Isobe ,  Susumu Okazaki ,  Koichiro Tanaka ,  Yoshiaki Yamamoto ,  Koji Dairiki ,  Tomoko Tamura

IPC: H01L21/00 ,  H01L21/76

CPC classification number: H01L27/1266 ,  H01L21/6835 ,  H01L24/83 ,  H01L27/1214 ,  H01L27/1218 ,  H01L2221/6835 ,  H01L2221/68368 ,  H01L2224/83 ,  H01L2924/01029 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00

Abstract: It is an object of the present invention to provide a method for manufacturing a semiconductor device, capable of keeping a peeling layer from being peeled from a substrate in the phase before the completion of a semiconductor element and peeling a semiconductor element rapidly. It is considered that a peeling layer tends to be peeled from a substrate because the stress is applied to a peeling layer due to the difference in thermal expansion coefficient between a substrate and a peeling layer, or because the volume of a peeling layer is reduced and thus the stress is applied thereto by crystallization of the peeling layer due to heat treatment. Therefore, according to one feature of the invention, the adhesion of a substrate and a peeling layer is enhanced by forming an insulating film (buffer film) for relieving the stress on the peeling layer between the substrate and the peeling layer before forming the peeling layer over the substrate.

Abstract translation: 本发明的目的是提供一种制造半导体器件的方法，该半导体器件的制造方法能够在半导体元件完成之前相位保持剥离层从基板剥离并快速剥离半导体元件。 由于衬底和剥离层之间的热膨胀系数的差异，或者由于剥离层的体积减小，由于将剥离层施加到剥离层上，因此认为剥离层倾向于剥离， 因此通过热处理使剥离层结晶而施加应力。 因此，根据本发明的一个特征，通过在形成剥离层之前形成用于缓解基板和剥离层之间的剥离层上的应力的绝缘膜（缓冲膜），增强了基板和剥离层的粘附性 在基板上。

公开(公告)号：US07692194B2

公开(公告)日：2010-04-06

申请号：US12015362

申请日：2008-01-16

Applicant: Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo

Inventor： Shunpei Yamazaki ,  Atsuo Isobe ,  Hiromichi Godo

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L29/78621 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having a novel structure by which the operating characteristics and reliability are improved and a manufacturing method thereof. An island-shaped semiconductor layer provided over a substrate, including a channel formation region provided between a pair of impurity regions; a first insulating layer provided so as to be in contact with the side surface of the semiconductor layer; a gate electrode provided over the channel formation region so as to get across the semiconductor layer; and a second insulating layer provided between the channel formation region and the gate electrode are included. The semiconductor layer is locally thinned, the channel formation region is provided in the thinned region, and the second insulating layer covers the first insulating layer provided on the side surface of the semiconductor layer at least in the region which overlaps with the gate electrode.

Abstract translation: 具有改善其操作特性和可靠性的新颖结构的半导体器件及其制造方法。 一种岛状半导体层，设置在衬底上，包括设置在一对杂质区之间的沟道形成区; 设置成与半导体层的侧表面接触的第一绝缘层; 栅电极，设置在所述沟道形成区上方以穿过所述半导体层; 并且包括设置在沟道形成区域和栅电极之间的第二绝缘层。 半导体层被局部变薄，沟道形成区域设置在减薄区域中，并且第二绝缘层至少在与栅电极重叠的区域中覆盖设置在半导体层的侧表面上的第一绝缘层。

公开(公告)号：US20100081251A1

公开(公告)日：2010-04-01

申请号：US12557545

申请日：2009-09-11

Applicant: Atsuo ISOBE ,  Junpei MOMO ,  Naoki OKUNO

Inventor： Atsuo ISOBE ,  Junpei MOMO ,  Naoki OKUNO

IPC: H01L21/762

CPC classification number: H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L27/1222 ,  H01L29/66772

Abstract: A single crystal semiconductor substrate is irradiated with accelerated ions to form an embrittled region in the single crystal semiconductor substrate. The single crystal semiconductor substrate and a base substrate are bonded to each other with an insulating layer interposed therebetween. The single crystal semiconductor substrate is separated at the embrittled region to form a semiconductor layer over the base substrate. Heat treatment is performed to reduce defects in the semiconductor layer. The semiconductor layer is then irradiated with laser light.

Abstract translation: 用单一晶体半导体衬底照射加速离子以在单晶半导体衬底中形成脆化区域。 单晶半导体衬底和基底衬底之间具有绝缘层而彼此接合。 在脆化区域分离单晶半导体衬底，以在基底衬底上形成半导体层。 进行热处理以减少半导体层中的缺陷。 然后用激光照射半导体层。

公开(公告)号：US20090098720A1

公开(公告)日：2009-04-16

申请号：US12334589

申请日：2008-12-15

Applicant: Atsuo ISOBE ,  Satoshi MURAKAMI ,  Tamae TAKANO ,  Shunpei YAMAZAKI

Inventor： Atsuo ISOBE ,  Satoshi MURAKAMI ,  Tamae TAKANO ,  Shunpei YAMAZAKI

IPC: H01L21/28 ,  H01L21/31

CPC classification number: H01L29/66757 ,  H01L27/12 ,  H01L27/1248 ,  H01L29/42384

Abstract: A manufacturing method of a semiconductor device of the present invention includes the steps of forming a first insulating film over a substrate, forming a semiconductor film over the first insulating film, oxidizing or nitriding the semiconductor film by conducting a plasma treatment to the semiconductor film under a condition of an electron density of 1×1011 cm−3 or more and 1×1013 cm−3 or less and an electron temperature of 0.5 eV or more and 1.5 eV or less, using a high frequency wave, forming a second insulating film to cover the semiconductor film, forming a gate electrode over the second insulating film, forming a third insulating film to cover the gate electrode, and forming a conductive film over the third insulating film.

Abstract translation: 本发明的半导体器件的制造方法包括以下步骤：在衬底上形成第一绝缘膜，在第一绝缘膜上形成半导体膜，通过对半导体膜进行等离子体处理来对半导体膜进行氧化或氮化 使用高频波，电子密度为1×10 11 cm -3以上且1×10 13 cm -3以下，电子温度为0.5eV以上且1.5eV以下的条件，形成覆盖半导体的第2绝缘膜 在所述第二绝缘膜上形成栅电极，形成第三绝缘膜以覆盖所述栅电极，以及在所述第三绝缘膜上形成导电膜。

公开(公告)号：US20090014799A1

公开(公告)日：2009-01-15

申请号：US12216567

申请日：2008-07-08

Applicant: Atsuo Isobe

Inventor： Atsuo Isobe

IPC: H01L27/08 ,  H01L21/30

CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78603

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. A semiconductor device comprises a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over a substrate having an insulating surface, a first gate insulating layer over the first single-crystal semiconductor layer, a gate electrode over the first gate insulating layer, a first interlayer insulating layer over the first gate insulating layer, a second gate insulating layer over the gate electrode and the first interlayer insulating layer, and a second single-crystal semiconductor layer including a second channel formation region and a second impurity region over the second gate insulating layer. The first channel formation region, the gate electrode, and the second channel formation region are overlapped with each other.

Abstract translation: 提供半导体器件和半导体器件的制造方法。 半导体器件包括：第一单晶半导体层，包括在具有绝缘表面的衬底上的第一沟道形成区和第一杂质区;在第一单晶半导体层上方的第一栅绝缘层，第一单晶半导体层上的栅电极 栅极绝缘层，第一栅极绝缘层上的第一层间绝缘层，栅极电极和第一层间绝缘层之上的第二栅极绝缘层，以及包括第二沟道形成区域和第二杂质的第二单晶半导体层 区域。 第一沟道形成区域，栅极电极和第二沟道形成区域彼此重叠。

公开(公告)号：US07449376B2

公开(公告)日：2008-11-11

申请号：US11120992

申请日：2005-05-04

Applicant: Atsuo Isobe ,  Tatsuya Arao

Inventor： Atsuo Isobe ,  Tatsuya Arao

IPC: H01L21/84

CPC classification number: H01L21/02672 ,  H01L21/02686 ,  H01L21/2022 ,  H01L21/2026 ,  H01L27/12 ,  H01L27/1277 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78624 ,  H01L29/78645 ,  H01L29/78675 ,  H01L29/78678

Abstract: An object of the present invention is to form a channel formation region, or a TFT formation region, using one crystal aggregate (domain) by controlling crystal location and size, thus suppressing TFT variations. According to the present invention, laser irradiation is performed selectively on an amorphous silicon film in the periphery of a channel formation region, or the periphery of a TFT formation region containing a channel formation region, source and drain region, and the like. Each TFT formation region is isolated, a metallic element for promoting crystallization (typically Ni) is added, and heat treatment is performed, thus making it possible to arbitrarily determine the locations of crystal aggregates (domains). It becomes possible to suppress variations in the TFTs by arbitrarily controlling the crystal aggregate (domain) locations.

Abstract translation: 本发明的目的是通过控制晶体位置和尺寸来形成使用一个晶体聚集体（畴）的沟道形成区域或TFT形成区域，从而抑制TFT变化。 根据本发明，在沟道形成区域的外围的非晶硅膜或包含沟道形成区域，源极和漏极区域的TFT形成区域的周边上的选择性地进行激光照射。 每个TFT形成区被隔离，加入用于促进结晶的金属元素（通常为Ni），并且进行热处理，从而可以任意地确定晶体聚集体（畴）的位置。 可以通过任意地控制晶体聚集体（畴）位置来抑制TFT的变化。

公开(公告)号：US20080272376A1

公开(公告)日：2008-11-06

申请号：US12170588

申请日：2008-07-10

Applicant: Tatsuya Arao ,  Atsuo Isobe ,  Toru Takayama

Inventor： Tatsuya Arao ,  Atsuo Isobe ,  Toru Takayama

IPC: H01L33/00

CPC classification number: G02F1/133305 ,  G02F1/1362 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/3244 ,  H01L29/66742 ,  H01L29/78603

Abstract: In a semiconductor device having a substrate which has a metal surface, an insulating film which is formed on the substrate having the metal surface, and a pixel unit which is formed on the insulating film; the pixel unit includes a TFT, and wiring lines connected with the TFT, and a storage capacitor is constituted by the substrate (11) having the metal surface, the insulating film (12), and the wiring line (21). As the insulating film is thinner, and as the area of a region where the insulating film and the wiring line lie in contact is larger, the storage capacitor is endowed with a larger capacity.

Abstract translation: 在具有金属表面的基板的半导体器件中，形成在具有金属表面的基板上的绝缘膜和形成在绝缘膜上的像素单元; 像素单元包括TFT和与TFT连接的布线，并且存储电容器由具有金属表面的基板（11），绝缘膜（12）和布线（21）构成。 由于绝缘膜更薄，并且随着绝缘膜和布线接触的区域的面积较大，所以存储电容器具有较大的容量。

公开(公告)号：US20080179599A1

公开(公告)日：2008-07-31

申请号：US11876429

申请日：2007-10-22

Applicant: Tetsuji YAMAGUCHI ,  Atsuo Isobe ,  Satoru Saito

Inventor： Tetsuji YAMAGUCHI ,  Atsuo Isobe ,  Satoru Saito

IPC: H01L27/14

CPC classification number: H01L27/1259 ,  H01L27/1214

Abstract: A salicide process is conducted to a thin film integrated circuit without worrying about damages to a glass substrate, and thus, high-speed operation of a circuit can be achieved. A base metal film, an oxide and a base insulating film are formed over a glass substrate. A TFT having a sidewall is formed over the base insulating film, and a metal film is formed to cover the TFT. Annealing is conducted by RTA or the like at such a temperature that does not cause shrinkage of the substrate, and a high-resistant metal silicide layer is formed in source and drain regions. After removing an unreacted metal film, laser irradiation is conducted for the second annealing; therefore a silicide reaction proceeds and the high-resistant metal silicide layer becomes a low-resistant metal silicide layer. In the second annealing, a base metal film absorbs and accumulates heat of the laser irradiation, and a semiconductor layer is supplied with beat of the base metal film in addition to heat of the laser irradiation, thereby enhancing efficiency of the silicide reaction in the source and drain regions.

Abstract translation: 对薄膜集成电路进行自对准处理，而不用担心对玻璃基板的损坏，因此可以实现电路的高速操作。 在玻璃基板上形成贱金属膜，氧化物和基底绝缘膜。 在基底绝缘膜上形成具有侧壁的TFT，并且形成覆盖TFT的金属膜。 在不会引起基板收缩的温度下由RTA等进行退火，在源极和漏极区域形成高阻金属硅化物层。 在除去未反应的金属膜之后，对第二次退火进行激光照射; 因此进行硅化物反应，高阻金属硅化物层变成低电阻金属硅化物层。 在第二退火中，贱金属膜吸收并累积激光照射的热量，并且除了激光照射的热量之外，还向半导体层供给贱金属膜的节拍，从而提高源的硅化物反应的效率 和漏区。

公开(公告)号：US07344925B2

公开(公告)日：2008-03-18

申请号：US11064820

申请日：2005-02-25

Applicant: Kiyoshi Kato ,  Toshihiko Saito ,  Atsuo Isobe ,  Toru Takayama ,  Junya Maruyama ,  Yuugo Goto ,  Yumiko Ohno

Inventor： Kiyoshi Kato ,  Toshihiko Saito ,  Atsuo Isobe ,  Toru Takayama ,  Junya Maruyama ,  Yuugo Goto ,  Yumiko Ohno

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/331

CPC classification number: H01L29/78696 ,  H01L27/12 ,  H01L27/1281 ,  H01L29/66757 ,  H01L29/78675 ,  H01L2221/68368

Abstract: An object of the present invention is to provide a semiconductor device formed by laser crystallization by which formation of grain boundaries in the TFT channel formation region can be avoided, and a method of manufacturing the same. Still another object of the present invention is to provide a method of designating the semiconductor device. The present invention relates to a semiconductor device with a plurality of cells each having a plurality of TFTs that have the same channel length direction, in which the plural cells form a plurality of columns along the channel length direction, in which an island-like semiconductor film of each of the plural TFTs is crystallized by laser light running in the channel length direction, in which a channel formation region of the island-like semiconductor film is placed on a depressive portion of a base film that has a rectangular or stripe pattern concave and convex with the channel length direction matching the longitudinal direction of the depressive portion, and in which a plurality of wires for electrically connecting the plural cells with one another are formed between the plural columns.

Abstract translation: 本发明的目的是提供一种通过激光晶化形成的半导体器件及其制造方法，可以避免TFT沟道形成区域中的晶界的形成。 本发明的另一个目的是提供一种指定半导体器件的方法。 本发明涉及具有多个单元的半导体器件，每个单元具有多个具有相同沟道长度方向的TFT，其中多个单元沿着沟道长度方向形成多个列，其中岛状半导体 通过在沟道长度方向上行进的激光，使多个TFT中的每一个的膜结晶，其中岛状半导体膜的沟道形成区域被放置在基膜的具有矩形或条纹图案凹部的凹部 并且其中通道长度方向与凹陷部分的纵向相匹配的凸起，并且其中在多个柱之间形成有用于彼此电连接多个单元的多根导线。

公开(公告)号：US07312473B2

公开(公告)日：2007-12-25

申请号：US10329993

申请日：2002-12-27

Applicant: Jun Koyama ,  Atsuo Isobe ,  Hiroshi Shibata ,  Shunpei Yamazaki

Inventor： Jun Koyama ,  Atsuo Isobe ,  Hiroshi Shibata ,  Shunpei Yamazaki

IPC: H01L29/00 ,  H01L29/94 ,  H01L33/00

CPC classification number: H01L29/78696 ,  H01L27/1296 ,  H01L27/3244 ,  H01L29/66757 ,  H01L29/78675

Abstract: In display devices using thin film transistors, a graphoepitaxy is used for a semiconductor layer crystallizing process. Thus, a display device in which crystallinity is improved, a variation in characteristics of thin film transistors is reduced, display nonuniformity is less, and a display quality is superior is provided. Steps are formed on a substrate in advance and an amorphous silicon film is formed thereon, and then laser crystallization is conducted in a direction perpendicular to the steps.

Abstract translation: 在使用薄膜晶体管的显示装置中，使用石墨刻蚀技术进行半导体层结晶工艺。 因此，结晶度提高的显示装置，薄膜​​晶体管的特性变化减小，显示不均匀性低，显示质量优异。 预先在基板上形成台阶，在其上形成非晶硅膜，然后在与台阶垂直的方向上进行激光结晶。