公开(公告)号：US08275805B2

公开(公告)日：2012-09-25

申请号：US12732392

申请日：2010-03-26

Applicant: Jatin Chhugani ,  Bryan Catanzaro ,  Sanjeev Kumar ,  Changkyu Kim ,  Nadathur Rajagopalan Satish

Inventor： Jatin Chhugani ,  Bryan Catanzaro ,  Sanjeev Kumar ,  Changkyu Kim ,  Nadathur Rajagopalan Satish

IPC: G06F17/30

CPC classification number: G06T15/00 ,  G06T13/00 ,  G06T17/005 ,  G06T2200/28

Abstract: A method of decreasing a total computation time for a visual simulation loop includes sharing a common data structure across each phase of the visual simulation loop by adapting the common data structure to a requirement for each particular phase prior to performing a computation for that particular phase.

Abstract translation: 减少可视化仿真循环的总计算时间的方法包括通过在对该特定阶段执行计算之前通过将公共数据结构适应于每个特定阶段的需求来共享视觉仿真循环的每个阶段的公共数据结构。

公开(公告)号：US08180997B2

公开(公告)日：2012-05-15

申请号：US12166439

申请日：2008-07-02

Applicant: Douglas C. Burger ,  Stephen W. Keckler ,  Robert McDonald ,  Paul Gratz ,  Nitya Ranganathan ,  Lakshminarasimhan Sethumadhavan ,  Karthikevan Sankaralingam ,  Ramadass Nagarajan ,  Changkyu Kim ,  Haiming Liu

Inventor： Douglas C. Burger ,  Stephen W. Keckler ,  Robert McDonald ,  Paul Gratz ,  Nitya Ranganathan ,  Lakshminarasimhan Sethumadhavan ,  Karthikevan Sankaralingam ,  Ramadass Nagarajan ,  Changkyu Kim ,  Haiming Liu

IPC: G06F15/76

CPC classification number: G06F9/3885 ,  G06F9/3836 ,  G06F9/3897 ,  G06F12/0875 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

Abstract: A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.

Abstract translation: 一种用于动态组成处理器内核以形成逻辑处理器的方法，系统和计算机程序产品。 处理器核心是可组合的，因为处理器核心被动态地分配以形成逻辑处理器来处理操作状态的改变。 一旦检测到操作状态的改变，则可以触发一种机制来将一个或多个处理器核重组到逻辑处理器中以处理操作状态的变化。 可以执行关于如何重组一个或多个处理器核来处理操作状态的变化的分析。 在分析之后，将一个或多个处理器核重新组合到逻辑处理器中以处理操作状态的改变。 通过动态分配处理器核来处理运行状态的变化，提高了性能和功率效率。

公开(公告)号：US20110161060A1

公开(公告)日：2011-06-30

申请号：US12655362

申请日：2009-12-29

Applicant: Changkyu Kim ,  Stephen J. Guy ,  Anthony-Trung D. Nguyen ,  Daehyun Kim ,  Jatin Chhugani

Inventor： Changkyu Kim ,  Stephen J. Guy ,  Anthony-Trung D. Nguyen ,  Daehyun Kim ,  Jatin Chhugani

IPC: G06F17/11 ,  G06G7/60

CPC classification number: G06T13/40 ,  G06T19/00 ,  G06T2210/21

Abstract: A method of computing a collision-free velocity (117, 217) for an agent (110) in a crowd simulation environment (100) comprises identifying a quadratic optimization problem that corresponds to the collision-free velocity, and finding an exact solution for the quadratic optimization problem by using a geometric approach.

Abstract translation: 在人群模拟环境（100）中计算用于代理（110）的无碰撞速度（117,217）的方法包括识别对应于无碰撞速度的二次优化问题，并且为 通过使用几何方法的二次优化问题。

公开(公告)号：US20110138122A1

公开(公告)日：2011-06-09

申请号：US12630826

申请日：2009-12-03

Applicant: Christopher J. Hughes ,  Yen-Kuang Chen ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Anthony-Trung D. Nguyen ,  Nadathur Rajagopalan Satish

Inventor： Christopher J. Hughes ,  Yen-Kuang Chen ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Anthony-Trung D. Nguyen ,  Nadathur Rajagopalan Satish

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0802 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

Abstract translation: 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。

公开(公告)号：US20110025700A1

公开(公告)日：2011-02-03

申请号：US12512284

申请日：2009-07-30

Applicant: Victor W. Lee ,  Mikhail Smelyanskiy ,  Yen-Kuang Chen ,  Jatin Chhugani ,  Jose Gonzalez ,  Changkyu Kim ,  Ganesh S. Dasika

Inventor： Victor W. Lee ,  Mikhail Smelyanskiy ,  Yen-Kuang Chen ,  Jatin Chhugani ,  Jose Gonzalez ,  Changkyu Kim ,  Ganesh S. Dasika

IPC: G09G5/00

CPC classification number: G06T1/20 ,  G06T15/005 ,  G09G5/363

Abstract: An interpolation unit, such as may be found in a texture unit or texture sampler, may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to an interpolation unit. The interpolation unit may use linear interpolators in order to perform the dot product calculations.

Abstract translation: 可以使用诸如在纹理单元或纹理采样器中可以找到的内插单元来执行诸如点积的通用数学计算。 这使得一些通用计算和操作能够从中央处理单元卸载到内插单元。 内插单元可以使用线性内插器来执行点积计算。

公开(公告)号：US20100138607A1

公开(公告)日：2010-06-03

申请号：US12315442

申请日：2008-12-03

Applicant: Christopher J. Hughes ,  Changkyu Kim ,  Yen-Kuang Chen

Inventor： Christopher J. Hughes ,  Changkyu Kim ,  Yen-Kuang Chen

IPC: G06F12/08

CPC classification number: G06F12/0828 ,  G06F12/0822

Abstract: In one embodiment, the present invention includes a directory of a private cache hierarchy to maintain coherency between data stored in the cache hierarchy, where the directory is to enable concurrent cache-to-cache transfer of data to two private caches. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括专用高速缓存层级的目录，以保持存储在高速缓存层级中的数据之间的一致性，其中目录是启用数据到两个私有高速缓存的缓存到高速缓存的传输。 描述和要求保护其他实施例。

公开(公告)号：US20100073368A1

公开(公告)日：2010-03-25

申请号：US12234988

申请日：2008-09-22

Applicant: Changkyu Kim ,  Jatin Chhugani ,  Christian Bienia ,  Daehyun Kim ,  Anthony Nguyen ,  Sanjeev Kumar

Inventor： Changkyu Kim ,  Jatin Chhugani ,  Christian Bienia ,  Daehyun Kim ,  Anthony Nguyen ,  Sanjeev Kumar

IPC: G06T15/40 ,  G06T15/00

CPC classification number: G06T15/40

Abstract: Methods and systems to determine view cell occlusion, including to project objects of a 3-dimensional graphics environment to a 2-dimensional image plane with respect to the view point, to reduce sizes of corresponding object images, to generate an occluder map from the reduced-size object images, to compare at least a portion of the object images to the occluder map, and to identify an object as occluded with respect to the view cell when pixel depth values of the object image are greater than corresponding pixel depth values of the occluder map. Methods and systems to reduce an object image size include methods and systems to nullify pixel depth values within a radius of an edge pixel, and to determine the radius as a distance from the edge pixel to a second pixel so that a line between the view point and the second pixel is parallel with one or more of a line and a plane that is tangential to a sphere enclosing the view cell and a point on the object that corresponds to the edge pixel.

Abstract translation: 确定观察细胞闭塞的方法和系统，包括将三维图形环境的对象相对于视点投影到二维图像平面，以减小相应对象图像的大小，从缩小的图像生成闭塞图 将对象图像的尺寸调整为将至少一部分对象图像与遮挡物图进行比较，并且当对象图像的像素深度值大于对象图像的对应像素深度值时，识别相对于视图单元被遮挡的对象 封堵器图。 减少对象图像尺寸的方法和系统包括使边缘像素的半径内的像素深度值无效的方法和系统，并且将半径确定为距离边缘像素到第二像素的距离，使得视点 并且第二像素平行于与包围视图单元的球体相切的线和平面以及与边缘像素对应的物体上的点的一个或多个。

公开(公告)号：US09299392B2

公开(公告)日：2016-03-29

申请号：US14055061

申请日：2013-10-16

Applicant: Jaekyu Lee ,  Changkyu Kim

Inventor： Jaekyu Lee ,  Changkyu Kim

IPC: G11C5/06 ,  H01L27/105 ,  G11C13/00 ,  H01L27/02 ,  H01L27/22 ,  H01L43/08 ,  H01L45/00 ,  H01L27/24 ,  G11C7/18

CPC classification number: G11C5/063 ,  G11C7/18 ,  G11C13/0002 ,  G11C2213/82 ,  H01L27/0207 ,  H01L27/228 ,  H01L27/2436 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: Semiconductor memory devices include unit cells two-dimensionally arranged along rows and columns in one cell array block. The unit cells are classified into a plurality of cell subgroups, and each of the cell subgroups includes the unit cells constituting a plurality of the rows. Each of the unit cells includes a selection element and a data storage part. A word line is connected to gate electrodes of selection elements of the unit cells constituting each column. Bit lines are connected to data storage parts of the unit cells constituting the rows. A source line, parallel to the bit line, is electrically connected to source terminals of the selection elements of the unit cells in each cell subgroup. The source line is parallel to the bit line. A distance between the source line and the select bit line is equal to a distance between the bit lines adjacent to each other.

Abstract translation: 半导体存储器件包括在一个单元阵列块中沿行和列二维排列的单位单元。 单元单元被分类为多个单元子组，并且每个单元子组包括构成多行的单元单元。 每个单位单元包括选择单元和数据存储单元。 字线连接到构成每列的单元电池的选择元件的栅电极。 位线连接到构成行的单位单元的数据存储部分。 平行于位线的源极线电连接到每个电池子组中的单元电池的选择元件的源极端子。 源极线与位线平行。 源极线和选择位线之间的距离等于彼此相邻的位线之间的距离。

公开(公告)号：US20140337580A1

公开(公告)日：2014-11-13

申请号：US14337174

申请日：2014-07-21

Applicant: CHRISTOPHER J. HUGHES ,  YEN-KUANG CHEN ,  CHANGKYU KIM ,  DAEHYUN KIM ,  VICTOR W. LEE ,  ANTHONY-TRUNG D. NGUYEN ,  NADATHUR RAJAGOPALAN SATISH

Inventor： CHRISTOPHER J. HUGHES ,  YEN-KUANG CHEN ,  CHANGKYU KIM ,  DAEHYUN KIM ,  VICTOR W. LEE ,  ANTHONY-TRUNG D. NGUYEN ,  NADATHUR RAJAGOPALAN SATISH

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0802 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

Abstract translation: 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。

公开(公告)号：US20140176590A1

公开(公告)日：2014-06-26

申请号：US14054933

申请日：2013-10-16

Applicant: Victor W. Lee ,  Mikhail Smelyanskiy ,  Ganesh S. Dasika ,  Jose Gonzalez ,  Jatin Chhugani ,  Yen-Kuang Chen ,  Changkyu Kim ,  Julio Gago ,  Santiago Galan ,  Victor Moya Del Barrio

Inventor： Victor W. Lee ,  Mikhail Smelyanskiy ,  Ganesh S. Dasika ,  Jose Gonzalez ,  Jatin Chhugani ,  Yen-Kuang Chen ,  Changkyu Kim ,  Julio Gago ,  Santiago Galan ,  Victor Moya Del Barrio

IPC: G06T11/00 ,  G06T1/00

CPC classification number: G06T11/001 ,  G06F17/16 ,  G06T1/00

Abstract: A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.

Abstract translation: 纹理单元可用于执行诸如点积的通用数学计算。 这使得一些通用计算和操作能够从中央处理单元卸载到纹理单元。 纹理单元可以使用线性内插器来执行点积计算。