公开(公告)号：US20050184388A1

公开(公告)日：2005-08-25

申请号：US10782365

申请日：2004-02-19

Applicant: Hsin-Ching Shih ,  Kang-Cheng Lin ,  Chao-Cheng Chen ,  Hun-Jan Tao

Inventor： Hsin-Ching Shih ,  Kang-Cheng Lin ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC: H01L23/48 ,  H01L23/58

CPC classification number: H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In accordance with the objective of the invention a new method is provided for the creation of a seal ring having dissimilar elements. The Critical Dimensions of the seal ring are selected with respect to the CD of other device features, such a seal vias, such that the difference in etch sensitivity between the created seal ring and the via holes is removed. All etch of the simultaneously etched features is completed at the same time, avoiding punch through of an underlying layer of etch stop material.

Abstract translation: 根据本发明的目的，提供了一种用于创建具有不同元件的密封环的新方法。 密封环的临界尺寸相对于其它装置特征（例如密封通孔）的CD被选择，使得所产生的密封环和通孔之间的蚀刻敏感性的差异被去除。 同时蚀刻的特征的所有蚀刻同时完成，避免冲蚀下一层蚀刻停止材料。

公开(公告)号：US06737345B1

公开(公告)日：2004-05-18

申请号：US10238290

申请日：2002-09-10

Applicant: Kang-Cheng Lin ,  Chin-Chiu Hsia

Inventor： Kang-Cheng Lin ,  Chin-Chiu Hsia

IPC: H01L2144

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabrication used for semiconductor integrated circuit devices to define a thin copper fuse at a top via opening, in a partial etch, dual damascene integration scheme, efficiently reducing top metal thickness in a fusible link, for the purpose of laser ablation. Some advantages of the method are: (a) avoids copper fuse contact to low dielectric material, which is subject to the thermal shock of laser ablation, (b) increases insulating material thickness over the fuse using better thickness control, and most importantly, (c) reduces the copper fuse thickness, for easy laser ablation of the copper fuse, and finally, (d) uses USG, undoped silicate glass to avoid direct contact with low dielectric constant materials.

Abstract translation: 为了激光烧蚀的目的，用于半导体集成电路器件的半导体集成电路器件的方法在部分蚀刻双镶嵌集成方案中，在顶部通孔开口处限定薄铜熔丝，从而有效地降低可熔连接中的顶部金属厚度。 该方法的一些优点是：（a）避免铜熔丝与低介电材料接触，这受到激光烧蚀的热冲击，（b）使用更好的厚度控制增加保险丝上的绝缘材料厚度，最重要的是（ c）降低铜熔丝厚度，便于铜熔丝的激光烧蚀，最后，（d）使用USG，未掺杂的硅酸盐玻璃避免与低介电常数材料的直接接触。

公开(公告)号：US6093632A

公开(公告)日：2000-07-25

申请号：US206738

申请日：1998-12-07

Applicant: Kang-Cheng Lin

Inventor： Kang-Cheng Lin

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/311

CPC classification number: H01L21/7681

Abstract: A process for creating a metal filled, dual damascene opening, in a composite insulator layer, has been developed. The process features selective RIE procedures, used to create a wide diameter opening in an upper silicon oxide layer, and a narrow diameter opening in a lower silicon oxide layer. Small area, silicon nitride islands, or shapes, a component of the composite insulator layer, are used as a stop layer, during the selective RIE procedures. The use of small area, silicon nitride shapes, offers less composite insulator capacitance, than counterparts fabricated using larger area, silicon nitride stop layers.

Abstract translation: 已经开发了用于在复合绝缘体层中形成金属填充的双镶嵌开口的方法。 该工艺具有用于在上氧化硅层中形成宽直径开口的选择性RIE程序和在下部氧化硅层中的窄直径开口。 在选择性RIE程序期间，复合绝缘体层的小面积，氮化硅岛或形状被用作停止层。 与使用较大面积的氮化硅阻挡层制造的对应物相比，使用小面积的氮化硅形状提供较少的复合绝缘体电容。

公开(公告)号：US5864150A

公开(公告)日：1999-01-26

申请号：US82778

申请日：1998-05-21

Applicant: Kang-Cheng Lin

Inventor： Kang-Cheng Lin

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L29/66765 ,  H01L29/78669 ,  H01L29/78678

Abstract: The present invention discloses a hybrid polysilicon/amorphous silicon TFT device for switching a LCD and a method for fabrication wherein a n.sup.+ doped amorphous silicon layer is advantageously used as a mask during a laser annealing process such that only a selected portion of a hydrogenated amorphous silicon layer is converted to a crystalline structure while other portions retain their amorphous structure. As a result, a polysilicon TFT and at least one amorphous silicon TFT are formed in the same structure and the benefits of both a polysilicon TFT and amorphous silicon TFT such as a high charge current and a low leakage current are retained in the hybrid structure.

Abstract translation: 本发明公开了一种用于切换LCD的混合多晶硅/非晶硅TFT器件及其制造方法，其中在激光退火工艺期间有利地使用n +掺杂非晶硅层作为掩模，使得只有选定部分的氢化非晶硅 层转化为晶体结构，而其它部分保留其非晶结构。 结果，在相同的结构中形成多晶硅TFT和至少一个非晶硅TFT，并且在混合结构中保留诸如高充电电流和低漏电流的多晶硅TFT和非晶硅TFT的优点。

公开(公告)号：US5811325A

公开(公告)日：1998-09-22

申请号：US775603

申请日：1996-12-31

Applicant: Kang-Cheng Lin ,  Hong-Jye Hong

Inventor： Kang-Cheng Lin ,  Hong-Jye Hong

IPC: H01L21/336 ,  H01L29/786 ,  H01L21/00 ,  H01L21/84

CPC classification number: H01L29/66765 ,  H01L29/78618

Abstract: The present invention includes forming a conductive layer on a substrate. Portions of the conductive layer are removed using a first photoresist layer as a mask. A first oxide layer is formed over the conductive layer and the substrate, and an amorphous silicon layer is then formed on the first oxide layer. After annealing the amorphous silicon layer, thereby transforming amorphous silicon layer to a polysilicon layer, a second oxide layer is formed on the polysilicon layer. The second oxide layer is removed using a second photoresist layer as a mask. An amorphous silicon carbon layer is formed over the second oxide layer and the polysilicon layer, and a heavily-doped amorphous silicon carbon layer is formed on the amorphous silicon carbon layer. After annealing the heavily-doped amorphous silicon carbon layer and the amorphous silicon carbon layer, thereby transforming the heavily-doped amorphous silicon carbon layer to a heavily-doped polysilicon carbon layer, and transforming the amorphous silicon carbon layer to a polysilicon carbon layer, portions of the polysilicon carbon layer, the heavily-doped polysilicon carbon layer and the polysilicon layer are removed using a third photoresist layer as a mask.

Abstract translation: 本发明包括在基板上形成导电层。 使用第一光致抗蚀剂层作为掩模去除部分导电层。 在导电层和基板上形成第一氧化物层，然后在第一氧化物层上形成非晶硅层。 在非晶硅层退火之后，将非晶硅层转化为多晶硅层，在多晶硅层上形成第二氧化物层。 使用第二光致抗蚀剂层作为掩模去除第二氧化物层。 在第二氧化物层和多晶硅层上形成非晶硅碳层，在非晶硅碳层上形成重掺杂的非晶硅碳层。 在重掺杂非晶硅碳层和非晶硅碳层退火之后，将重掺杂非晶硅碳层转化为重掺杂多晶硅碳层，并将非晶硅碳层转化为多晶碳层， 的多晶硅碳层，使用第三光致抗蚀剂层作为掩模去除重掺杂多晶硅碳层和多晶硅层。

公开(公告)号：US5783843A

公开(公告)日：1998-07-21

申请号：US822225

申请日：1997-03-21

Applicant: Kang-Cheng Lin

Inventor： Kang-Cheng Lin

IPC: H01L21/336 ,  H01L21/84 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/78645 ,  H01L29/6675 ,  H01L29/66757 ,  H01L29/78621

Abstract: A method of fabricating a polycrystalline silicon thin-film transistor having two symmetrical lateral resistors is disclosed. Two sub-gates are formed along with a gate in the gate metal or polysilicon layer of the thin-film transistor. The two sub-gates that are located symmetrically on the two sides of the gate have equal distances to the gate. One sub-gate is near the drain of the thin film transistor and the other near the source. Two sections in the polycrystalline silicon layer of the thin film transistor are blocked by the two sub-gates and no impurity material is doped. The two undoped sections form the symmetrical lateral resistors of this invention. The lateral resistor near the drain decreases the electric field in the nearby depletion area when the thin-film transistor is switched off. The current leakage is reduced.

Abstract translation: 公开了一种制造具有两个对称横向电阻器的多晶硅薄膜晶体管的方法。 两个子栅极与薄膜晶体管的栅极金属或多晶硅层中的栅极一起形成。 对称地位于栅极两侧的两个子栅极具有与栅极相等的距离。 一个子栅极在薄膜晶体管的漏极附近，另一个靠近源极。 薄膜晶体管的多晶硅层中的两个部分被两个子栅极阻挡，并且不掺杂杂质材料。 两个未掺杂部分形成本发明的对称横向电阻器。 当薄膜晶体管关闭时，漏极附近的横向电阻减小了附近耗尽区域中的电场。 电流泄漏减少。

公开(公告)号：US08853068B2

公开(公告)日：2014-10-07

申请号：US13329877

申请日：2011-12-19

Applicant: Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

Inventor： Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，在第一区域的高k电介质层上形成覆盖层，形成第一金属层 在第一区域中的覆盖层和第二区域中的高k电介质之上，然后在第一区域中形成第一栅极堆叠，在第二区域中形成第二栅极叠层，保护第一栅极叠层中的第一金属层，同时 对所述第二栅极堆叠中的所述第一金属层进行处理工艺，以及在所述第一栅极堆叠中的所述第一金属层上方以及所述第二栅极堆叠中经处理的第一金属层之上形成第二金属层。

公开(公告)号：US20120225529A1

公开(公告)日：2012-09-06

申请号：US13465551

申请日：2012-05-07

Applicant: Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

Inventor： Chieh-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC: H01L21/336 ,  H01L21/425

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US08159035B2

公开(公告)日：2012-04-17

申请号：US11840365

申请日：2007-08-17

Applicant: Donald Y. Chao ,  Albert Chin ,  Ping-Fang Hung ,  Fong-Yu Yen ,  Kang-Cheng Lin ,  Kuo-Tai Huang

Inventor： Donald Y. Chao ,  Albert Chin ,  Ping-Fang Hung ,  Fong-Yu Yen ,  Kang-Cheng Lin ,  Kuo-Tai Huang

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L21/28185 ,  H01L21/28097 ,  H01L21/28202 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665

Abstract: A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device.

Abstract translation: 半导体结构包括难熔金属硅化物层; 在难熔金属硅化物层上的富硅难熔金属硅化物层; 和富硅难熔金属硅化物层上的富金属难熔金属硅化物层。 难熔金属硅化物层，富硅难熔金属硅化物层和富含金属的难熔金属硅化物层包括相同的难熔金属。 半导体结构形成金属氧化物半导体器件的栅电极的一部分。

公开(公告)号：US08105931B2

公开(公告)日：2012-01-31

申请号：US12424739

申请日：2009-04-16

Applicant: Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

Inventor： Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L29/49 ,  H01L29/51

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，在第一区域的高k电介质层上形成覆盖层，形成第一金属层 在第一区域中的覆盖层和第二区域中的高k电介质之上，然后在第一区域中形成第一栅极堆叠，在第二区域中形成第二栅极叠层，保护第一栅极叠层中的第一金属层，同时 对所述第二栅极堆叠中的所述第一金属层进行处理工艺，以及在所述第一栅极堆叠中的所述第一金属层上方以及所述第二栅极堆叠中经处理的第一金属层之上形成第二金属层。