公开(公告)号：US20160018866A1

公开(公告)日：2016-01-21

申请号：US14800629

申请日：2015-07-15

Applicant: Netlist, Inc.

Inventor： Scott H. Milton

IPC: G06F1/30 ,  G06F12/02 ,  G06F1/32 ,  G06F12/06

CPC classification number: G06F1/30 ,  G06F1/3275 ,  G06F11/00 ,  G06F11/1446 ,  G06F11/34

Abstract: A memory system is described. The memory system includes a plurality of memory subsystems. Further, the memory system includes a controller coupled with the plurality of memory subsystems. The memory system also includes a power module including a storage device configured to store information and the power module is detachably coupled with the controller.

Abstract translation: 描述了存储器系统。 存储器系统包括多个存储器子系统。 此外，存储器系统包括与多个存储器子系统耦合的控制器。 存储器系统还包括电源模块，其包括被配置为存储信息的存储设备，并且电源模块可拆卸地与控制器耦合。

公开(公告)号：US20140156919A1

公开(公告)日：2014-06-05

申请号：US14173219

申请日：2014-02-05

Applicant: Netlist, Inc.

Inventor： Chi-She Chen ,  Jeffrey C. Solomon ,  Scott H. Milton ,  Jayesh Bhakta

IPC: G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1072 ,  G06F11/1441 ,  G06F11/2015 ,  G06F12/00 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C5/141 ,  G11C5/143 ,  G11C7/1072 ,  G11C11/005 ,  G11C14/0018 ,  G11C29/52

Abstract: Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.

Abstract translation: 本文描述的某些实施例包括具有易失性存储器子系统，非易失性存储器子系统，耦合到非易失性存储器子系统的控制器和耦合到易失性存储器子系统的电路，到控制器以及主机的存储器系统 系统。 在第一操作模式中，电路可操作以选择性地将控制器与易失性存储器子系统隔离开，并且将易失性存储器子系统选择性地耦合到主机系统以允许在易失性存储器子系统和主机系统之间传送数据。 在第二操作模式中，电路可操作以选择性地将控制器耦合到易失性存储器子系统，以允许使用控制器在易失性存储器子系统和非易失性存储器子系统之间传送数据，并且该电路可操作以选择性地隔离 来自主机系统的易失性存储器子系统。

公开(公告)号：US20250094061A1

公开(公告)日：2025-03-20

申请号：US18899679

申请日：2024-09-27

Applicant: Netlist, Inc.

Inventor： Hyun LEE

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0815 ,  G06F12/0868

Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the nonvolatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals. The NV controller and the non-volatile memory can be mounted on the motherboard.

公开(公告)号：US20240221852A1

公开(公告)日：2024-07-04

申请号：US18402549

申请日：2024-01-02

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Soonju Choi

IPC: G11C29/10 ,  G11C29/12 ,  G11C5/04

CPC classification number: G11C29/10 ,  G11C29/12 ,  G11C5/04

Abstract: A memory module comprises memory devices, a data module and a control module. The memory module is operable in a first mode in which at least some of the memory devices are accessed by a system memory controller in a computer system for memory read and/or write operations at a memory access speed, the control module is configured to register address and control signals associated with the memory read and/or write operations, and the data module is configured to propagate data signals between the at least some of the memory devices and the memory controller. The memory module is further operable in a second mode in which the memory devices are not accessed by the system memory controller for memory read or write operations, and the data module is configured to communicate data signals with at least some of the memory devices at the memory access speed.

公开(公告)号：US12026397B2

公开(公告)日：2024-07-02

申请号：US18059966

申请日：2022-11-29

Applicant: Netlist, Inc.

Inventor： Jeekyoung Park ,  Jordan Horwich

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0659 ,  G06F3/0683

Abstract: A memory module according to some embodiments is operable in a computer system including a memory controller coupled to a memory channel. The memory module comprises a volatile memory subsystem, non-volatile (NV) memory subsystem and a module controller coupled to the volatile memory subsystem and the NV memory subsystem. The volatile memory subsystem includes dynamic random access memory (DRAM) devices and is configurable to communicate with the memory controller via the memory channel during memory read or write operations. The module controller is configured to output data strobe signals to accompany data from the volatile memory subsystem during a memory read operation and to output to accompany data strobes output by data buffers in response to data strobe signals from the memory controller during a system-initiated operation to transfer data from the NV memory subsystem to the volatile memory subsystem.

公开(公告)号：US11880319B2

公开(公告)日：2024-01-23

申请号：US17840593

申请日：2022-06-14

Applicant: Netlist, Inc.

Inventor： Hyun Lee

IPC: G06F12/00 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G06F9/445 ,  G06F13/24 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F12/06 ,  G11C5/00 ,  G11C16/26 ,  G11C29/00 ,  G11C29/44

CPC classification number: G06F13/1694 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/445 ,  G06F11/1068 ,  G06F12/0646 ,  G06F13/1668 ,  G06F13/24 ,  G11C5/04 ,  G11C7/1063 ,  G11C29/52 ,  G11C5/00 ,  G11C7/1066 ,  G11C16/26 ,  G11C29/78 ,  G11C2029/4402 ,  G11C2207/2254

Abstract: According to certain aspects, a memory subsystem is coupled to a memory controller of a host computer system via an interface. The memory subsystem comprises dynamic random access memory elements and a memory subsystem controller. During a normal memory read or write operation, the memory subsystem controller is configured to receive address and command signals associated with the memory read or write operations and to control the dynamic random access memory elements in accordance with the address and command signals. The memory subsystem controller is further configured to output via the open drain output a parity error signal in response to a parity error having occurred during the memory read or write operation. During an initialization operation, the memory subsystem controller is configured to output via the open train output a signal related to one or more parts of initialization operation sequences.

公开(公告)号：US20210374080A1

公开(公告)日：2021-12-02

申请号：US17336262

申请日：2021-06-01

Applicant: Netlist Inc.

Inventor： Jordan HORWICH ,  Jerry ALSTON ,  Chih-Cheh CHEN ,  Patrick LEE ,  Scott MILTON ,  Jeekyoung PARK

IPC: G06F13/16 ,  G06F12/0891 ,  G06F12/0862

Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.

公开(公告)号：US20210279194A1

公开(公告)日：2021-09-09

申请号：US17328019

申请日：2021-05-24

Applicant: Netlist, Inc.

Inventor： Chi-She Chen ,  Jeffrey C. Solomon ,  Scott H. Milton ,  Jayesh Bhakta

IPC: G06F13/28 ,  G06F12/02 ,  G06F13/16 ,  G06F1/18 ,  G06F12/06 ,  G06F13/42 ,  G11C7/10 ,  G11C14/00 ,  G06F3/06 ,  G06F13/40

Abstract: In certain embodiments, a memory module includes a printed circuit board (PCB) having an interface that couples it to a host system for provision of power, data, address and control signals. First, second, and third buck converters receive a pre-regulated input voltage and produce first, second and third regulated voltages. A converter circuit reduces the pre-regulated input voltage to provide a fourth regulated voltage. Synchronous dynamic random access memory (SDRAM) devices are coupled to one or more regulated voltages of the first, second, third and fourth regulated voltages, and a voltage monitor circuit monitors an input voltage and produces a signal in response to the input voltage having a voltage amplitude that is greater than a threshold voltage.

公开(公告)号：US20210271593A1

公开(公告)日：2021-09-02

申请号：US17202021

申请日：2021-03-15

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/00 ,  G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

Abstract: A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive N-bit-wide data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. Each respective data buffer includes a n-bit-wide (n

公开(公告)号：US20210240620A1

公开(公告)日：2021-08-05

申请号：US17141978

申请日：2021-01-05

Applicant: NETLIST, INC.

Inventor： Hyun Lee ,  Jayesh R. Bhakta

IPC: G06F12/0802 ,  G11C5/04 ,  G11C29/02 ,  G11C7/10

Abstract: A memory module is operable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals and a system clock from the memory controller and to output a module clock, module C/A signals and data buffer control signals. The module C/A signals are provided to memory devices organized in one or more ranks, while the data buffer control signals, together with the module clock, are provided to a plurality of buffer circuits corresponding to respective groups of memory devices and are used to control data paths in the buffer circuits. The plurality of buffer circuits include clock regeneration circuits to regenerate clock signals with programmable delays from the module clock. The regenerated clock signals are provided to respective groups of memory devices so as to locally sync the buffer circuits with respective groups of memory devices.