公开(公告)号：US07786376B2

公开(公告)日：2010-08-31

申请号：US11841629

申请日：2007-08-20

Applicant: Somnath Nag ,  Mehrdad Moslehi

Inventor： Somnath Nag ,  Mehrdad Moslehi

IPC: H01L31/04 ,  H01L21/00

CPC classification number: H01L31/03529 ,  H01L31/07 ,  Y02E10/50

Abstract: A Schottky contact photovoltaic energy conversion cell. The Schottky contact photovoltaic energy conversion cell comprises a flexible substrate and a first array of a plurality of closely-spaced microscale pillars connected to a first electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a first Schottky metal material with a work function selected for efficiently collecting photogenerated electrons. The Schottky contact photovoltaic energy conversion cell further comprises a second array of a plurality of closely-spaced microscale pillars connected to a second electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a second Schottky metal material with a work function selected for efficiently collecting photogenerated holes. The Schottky contact photovoltaic energy conversion cell further comprises a semiconductor absorber thin-film layer covering the first and second contacts and filling spaces among all the pillars, for creating photogenerated electrons and holes.

Abstract translation: 肖特基接触光伏能量转换电池。 肖特基接触光伏能量转换单元包括柔性基板和连接到第一电单元接触件的多个紧密间隔的微米柱的第一阵列。 柱和接触由具有选择用于有效收集光生电子的功函数的第一肖特基金属材料（或具有顶部）层形成。 肖特基接触光伏能量转换单元还包括连接到第二电池触点的多个紧密间隔的微小柱的第二阵列。 支柱和接触由具有选择用于有效收集光生孔的功函数的（或具有顶部）第二肖特基金属材料层形成。 肖特基接触光伏能量转换单元还包括覆盖所有第一和第二触点和填充空间的半导体吸收体薄膜层，用于产生光生电子和空穴。

公开(公告)号：US20080318441A1

公开(公告)日：2008-12-25

申请号：US12199402

申请日：2008-08-27

Applicant: Ajit Paranjpe ,  Somnath Nag

Inventor： Ajit Paranjpe ,  Somnath Nag

IPC: H01L21/762

CPC classification number: C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Abstract translation: 提供了一种用于无缝填充深沟槽结构的原位掺杂非晶硅的方法，其中第一填充以使得膜沉积从沟槽底部向上发生的方式进行，其中步骤覆盖良好地超过 100％。 在第二填充步骤中，改变沉积条件以减少掺杂剂对沉积速率的影响，并且沉积以超过第一填充的沉积速率的速率进行。 在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火， 在填充的沟槽内分布掺杂剂。 此后，可以执行附加步骤以完成电容器结构的形成。

公开(公告)号：US07446366B2

公开(公告)日：2008-11-04

申请号：US11420893

申请日：2006-05-30

Applicant: Ajit Paranjpe ,  Somnath Nag

Inventor： Ajit Paranjpe ,  Somnath Nag

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Abstract translation: 提供了一种无空隙填充深沟槽结构的原位掺杂非晶硅的方法，其中在硅烷比例的温度，压力和掺杂剂下进行第一次填充，使得从沉积的底部发生膜沉积 向上。 通过这个第一次填充，达到100％以上的步骤覆盖率。 在第二填充步骤中，在改变的条件下进行沉积，以减少掺杂剂对沉积速率的影响，由此以超过第一填充物的沉积速率的沉积速率完成沟槽填充。 在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火， 在填充的沟槽内分布掺杂剂。 此后，可以执行附加步骤以完成电容器结构的形成。

公开(公告)号：US20060128139A1

公开(公告)日：2006-06-15

申请号：US11011550

申请日：2004-12-14

Applicant: Ajit Paranjpe ,  Somnath Nag

Inventor： Ajit Paranjpe ,  Somnath Nag

IPC: H01L21/4763

CPC classification number: C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

公开(公告)号：US06214719B1

公开(公告)日：2001-04-10

申请号：US09408631

申请日：1999-09-30

Applicant: Somnath Nag

Inventor： Somnath Nag

IPC: H01L2176

CPC classification number: H01L21/7682

Abstract: Air-gap technology is introduced in the damascene scheme, reducing the capacitance between interconnect metal lines on an integrated circuit substrate, and ultimately enhancing the speed of the device. Reduction of extraneous signal energy (cross-talk) from traversing from one metal line to another is also realized. The method for implementing an air-gap filled dielectric between the interconnect metal lines involves depositing a first dielectric layer on the substrate at a predetermined height. Next the first dielectric is patterned and etched to form lines. A second dielectric layer is then deposited using air-gap technology, such that the second dielectric contains air-gaps between the first dielectric lines. These air-gaps are situated below the predetermined height of the first dielectric. The substrate is then polished so that the top surface of the first dielectric is exposed. The first dielectric lines are then etched and removed. A metal is deposited in place of the removed first dielectric lines, forming interconnect metal lines on the substrate having an air-gap filled dielectric therebetween. The air-gap filled dielectric has a dielectric constant on the order of k=1.9 to 2.5, which is significantly lower than that of the same dielectric material without the air-gap.

Abstract translation: 在镶嵌方案中引入气隙技术，减少集成电路基板上互连金属线之间的电容，最终提高器件的速度。 还实现了从一条金属线到另一条金属线的外部信号能量（串扰）的减少。 在互连金属线之间实现气隙填充电介质的方法包括在预定高度上在衬底上沉积第一电介质层。 接下来，对第一电介质进行图案化和蚀刻以形成线。 然后使用气隙技术沉积第二电介质层，使得第二电介质在第一介电线之间包含气隙。 这些气隙位于第一电介质的预定高度以下。 然后抛光衬底，使第一电介质的顶表面露出。 然后蚀刻并除去第一介质线。 沉积金属代替去除的第一介电线，在衬底上形成互补金属线，其间具有气隙填充电介质。 气隙填充电介质的介电常数为k = 1.9〜2.5，这明显低于没有气隙的相同介电材料的介电常数。

公开(公告)号：US20130056044A1

公开(公告)日：2013-03-07

申请号：US13566960

申请日：2012-08-03

Applicant: Kramadhati V. Ravi ,  Tirunelveli S. Ravi ,  Ashish Asthana ,  Somnath Nag

Inventor： Kramadhati V. Ravi ,  Tirunelveli S. Ravi ,  Ashish Asthana ,  Somnath Nag

IPC: H01L31/042 ,  H01L31/18 ,  H01L31/045

CPC classification number: H01L31/0504 ,  H01L31/02363 ,  H01L31/048 ,  H01L31/068 ,  H01L31/1896 ,  Y02E10/547

Abstract: Photovoltaic modules including a plurality of solar cells bonded to a module back sheet are described herein, wherein each solar cell includes a superstrate bonded to a front side of a photovoltaic device to facilitate handling of very thin photovoltaic devices during fabrication of the module. Modules may also include module front sheets and the solar cells may include bottom sheets. The modules may be made of flexible materials, and may be foldable. Fabrication processes include tabbing photovoltaic devices prior to attaching the individual superstrates.

Abstract translation: 这里描述了包括结合到模块背板的多个太阳能电池的光伏模块，其中每个太阳能电池包括结合到光伏器件的前侧的顶板，以便于在模块制造期间处理非常薄的光伏器件。 模块还可以包括模块前片，并且太阳能电池可以包括底片。 模块可以由柔性材料制成，并且可以是可折叠的。 制造工艺包括在连接各个覆盖物之前贴上光伏器件。

公开(公告)号：US20120040487A1

公开(公告)日：2012-02-16

申请号：US13208302

申请日：2011-08-11

Applicant: Ashish Asthana ,  Tirunelveli S. Ravi ,  Kramadhati V. Ravi ,  Somnath Nag

Inventor： Ashish Asthana ,  Tirunelveli S. Ravi ,  Kramadhati V. Ravi ,  Somnath Nag

IPC: H01L31/18

CPC classification number: H01L31/02245 ,  H01L31/02168 ,  H01L31/03921 ,  H01L31/068 ,  H01L31/1804 ,  H01L31/1892 ,  Y02E10/547 ,  Y02P70/521

Abstract: Methods of fabricating metal wrap through solar cells and modules for thin silicon solar cells, including epitaxial silicon solar cells, are described. These metal wrap through solar cells have a planar back contact geometry for the base and emitter contacts. Fabrication of a metal wrap through solar cell may comprise: providing a photovoltaic device attached at the emitter side of the device to a solar glass by an encapsulant, the device including busbars on the device emitter; forming vias through the device base and emitter, the vias terminating in the busbars; depositing a conformal dielectric film over the surface of the vias and the back surface of the base; removing portions of the conformal dielectric film from the ends of the vias for exposing the busbars and from field areas of the base; and forming separate electrical contacts to the busbars and the field areas on the back surface of the solar cell. The solar cells may comprise epitaxially deposited silicon and may include an epitaxially deposited back surface field.

Abstract translation: 描述了通过太阳能电池制造金属封套的方法和用于薄硅太阳能电池的模块，包括外延硅太阳能电池。 这些金属包裹太阳能电池具有用于基极和发射极触点的平面后接触几何形状。 通过太阳能电池制造金属卷可以包括：通过密封剂将装置的发射极侧附接到太阳能玻璃上的光伏器件，该器件包括器件发射极上的母线; 通过设备基座和发射器形成通孔，终端在母线中的通孔; 在通孔的表面和基底的后表面上沉积保形电介质膜; 从所述通孔的端部去除所述共形绝缘膜的部分，以暴露所述母线和所述基座的场区域; 并且形成与母线和太阳能电池背面上的场区分开的电接触。 太阳能电池可以包括外延沉积的硅并且可以包括外延沉积的背表面场。

公开(公告)号：US07713881B2

公开(公告)日：2010-05-11

申请号：US12199402

申请日：2008-08-27

Applicant: Ajit Paranjpe ,  Somnath Nag

Inventor： Ajit Paranjpe ,  Somnath Nag

IPC: H01L21/311

CPC classification number: C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in a way so that film deposition occurs from the bottom of the trench upwards, with step coverage well in excess of 100%. In a second fill step, deposition conditions are changed to reduce the impact of dopant on deposition rate, and deposition proceeds at a rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Abstract translation: 提供了一种用于无缝填充深沟槽结构的原位掺杂非晶硅的方法，其中第一填充以使得膜沉积从沟槽底部向上发生的方式进行，其中步骤覆盖良好地超过 100％。 在第二填充步骤中，改变沉积条件以减少掺杂剂对沉积速率的影响，并且沉积以超过第一填充的沉积速率的速率进行。 在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火， 在填充的沟槽内分布掺杂剂。 此后，可以执行附加步骤以完成电容器结构的形成。

公开(公告)号：US20060234470A1

公开(公告)日：2006-10-19

申请号：US11420893

申请日：2006-05-30

Applicant: Ajit Paranjpe ,  Somnath Nag

Inventor： Ajit Paranjpe ,  Somnath Nag

IPC: H01L21/76

CPC classification number: C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Abstract translation: 提供了一种无空隙填充深沟槽结构的原位掺杂非晶硅的方法，其中在硅烷比例的温度，压力和掺杂剂下进行第一次填充，使得从沉积的底部发生膜沉积 向上。 通过这个第一次填充，达到100％以上的步骤覆盖率。 在第二填充步骤中，在改变的条件下进行沉积，以减少掺杂剂对沉积速率的影响，由此以超过第一填充物的沉积速率的沉积速率完成沟槽填充。 在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火， 在填充的沟槽内分布掺杂剂。 此后，可以执行附加步骤以完成电容器结构的形成。

公开(公告)号：US06764952B1

公开(公告)日：2004-07-20

申请号：US10099232

申请日：2002-03-13

Applicant: Jengyi Yu ,  Ka Shun Wong ,  Sanjeev Jain ,  Somnath Nag ,  Haiying Fu ,  Atul Gupta ,  Bart J. Van Schravendijk

Inventor： Jengyi Yu ,  Ka Shun Wong ,  Sanjeev Jain ,  Somnath Nag ,  Haiying Fu ,  Atul Gupta ,  Bart J. Van Schravendijk

IPC: H01L2144

CPC classification number: H01L21/02126 ,  C23C16/325 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/28525 ,  H01L21/314 ,  H01L21/31633 ,  Y10S438/958

Abstract: Two sequential treatments within a chemical vapor deposition chamber, or within sequential chambers without a vacuum break, are performed on a copper layer to clean and passivate the copper surface prior to deposition of a copper diffusion barrier layer or a dielectric layer. The first treatment includes an ammonia, a hydrogen, or a hydrocarbon plasma cleaning of the copper surface followed by a short initiation of an organosilane precursor or a thin silicon nitride layer. A copper diffusion barrier layer may then be formed over the pretreated copper surface using an organosilane plasma, with or without a carbon dioxide or a carbon monoxide, or a silane with a nitrogen gas and an ammonia gas. Copper diffusion is retarded and film adhesion is improved for a dielectric layer or a copper diffusion barrier layer on the copper surface.

Abstract translation: 化学气相沉积室内或在没有真空断裂的连续室内的两个连续处理在铜层上进行，以在沉积铜扩散阻挡层或介电层之前对铜表面进行清洁和钝化。 第一种处理包括氨，氢或铜表面的烃等离子体清洗，随后有机硅烷前体或薄氮化硅层的短时间启动。 然后可以使用具有或不具有二氧化碳或一氧化碳的有机硅烷等离子体或具有氮气和氨气的硅烷在预处理的铜表面上形成铜扩散阻挡层。 对于铜表面上的电介质层或铜扩散阻挡层，延伸铜扩散并改善膜粘附。