公开(公告)号：US08999058B2

公开(公告)日：2015-04-07

申请号：US12774667

申请日：2010-05-05

Applicant: George D. Kamian ,  Somnath Nag ,  Subbu Tamilmani ,  Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Takao Yonehara

Inventor： George D. Kamian ,  Somnath Nag ,  Subbu Tamilmani ,  Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  Takao Yonehara

IPC: C30B1/10 ,  C25D11/32 ,  H01L31/18 ,  C25D17/00 ,  C25D17/06 ,  C25D11/00

CPC classification number: C25D11/32 ,  C25D11/005 ,  C25D17/001 ,  C25D17/06 ,  C25F3/12 ,  C25F7/00 ,  H01L31/1892 ,  Y02E10/50

Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further the disclosure is applicable to the general fields of Photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.

Abstract translation: 本公开使得能够高生产率地制造基于半导体的分离层（由单层或多层多孔半导体（例如多孔硅，包括单孔隙率或多孔度层构成），光反射器（由多层/多孔多孔半导体 孔隙度多孔半导体如多孔硅），用于防反射涂层的多孔半导体（例如多孔硅）的形成，钝化层和多结的多带隙太阳能电池（例如，通过形成可变带隙 晶体硅薄膜或晶圆太阳能电池上的多孔硅发射器）。 其他应用包括制造用于脱模和MEMS器件制造，膜形成和浅沟槽隔离（STI）多孔硅的MEMS分离和牺牲层（使用具有最佳孔隙率并随后氧化的多孔硅形成）。 此外，本公开可应用于光伏，MEMS（包括传感器和致动器）的独立或集成半导体微电子，半导体微电子芯片和光电子学的一般领域。

公开(公告)号：US20080047601A1

公开(公告)日：2008-02-28

申请号：US11841629

申请日：2007-08-20

Applicant: Somnath Nag ,  Mehrdad Moslehi

Inventor： Somnath Nag ,  Mehrdad Moslehi

IPC: H01L31/04 ,  H01L21/00

CPC classification number: H01L31/03529 ,  H01L31/07 ,  Y02E10/50

Abstract: A Schottky contact photovoltaic energy conversion cell. The Schottky contact photovoltaic energy conversion cell comprises a flexible substrate and a first array of a plurality of closely-spaced microscale pillars connected to a first electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a first Schottky metal material with a work function selected for efficiently collecting photogenerated electrons. The Schottky contact photovoltaic energy conversion cell further comprises a second array of a plurality of closely-spaced microscale pillars connected to a second electrical cell contact. The pillars and the contact are formed of (or having a top) layer of a second Schottky metal material with a work function selected for efficiently collecting photogenerated holes. The Schottky contact photovoltaic energy conversion cell further comprises a semiconductor absorber thin-film layer covering the first and second contacts and filling spaces among all the pillars, for creating photogenerated electrons and holes.

Abstract translation: 肖特基接触光伏能量转换电池。 肖特基接触光伏能量转换单元包括柔性基板和连接到第一电单元接触件的多个紧密间隔的微米柱的第一阵列。 柱和接触由具有选择用于有效收集光生电子的功函数的第一肖特基金属材料（或具有顶部）层形成。 肖特基接触光伏能量转换单元还包括连接到第二电池触点的多个紧密间隔的微小柱的第二阵列。 支柱和接触由具有选择用于有效收集光生孔的功函数的（或具有顶部）第二肖特基金属材料层形成。 肖特基接触光伏能量转换单元还包括覆盖所有第一和第二触点和填充空间的半导体吸收体薄膜层，用于产生光生电子和空穴。

公开(公告)号：US20070280526A1

公开(公告)日：2007-12-06

申请号：US11420960

申请日：2006-05-30

Applicant: Irfan Malik ,  Somnath Nag

Inventor： Irfan Malik ,  Somnath Nag

IPC: G06K9/00

CPC classification number: G01N21/9501 ,  G01N21/4738 ,  G06T7/001 ,  G06T2207/30148

Abstract: Various computer-implemented methods are provided. One computer-implemented method for determining information about a defect detected on a wafer after an immersion lithography (IL) process is performed on the wafer includes comparing inspection results for the defect to data in a defect library for different types of IL defects and determining the information about the defect based on results of the comparison. One computer-implemented method for binning defects detected on a wafer after an IL process is performed on the wafer includes comparing one or more characteristics of the defects to one or more characteristics of IL defects and one or more characteristics of non-IL defects. The method also includes binning the defects having one or more characteristics that substantially match the one or more characteristics of the IL defects and the non-IL defects in different groups.

Abstract translation: 提供了各种计算机实现的方法。 在晶片上执行浸没光刻（IL）处理之后，确定关于在晶片上检测到的缺陷的信息的计算机实现方法包括将缺陷的检查结果与不同类型的IL缺陷的缺陷库中的数据进行比较，并且确定 基于比较结果的缺陷信息。 在晶片上执行IL处理之后，在晶片上检测到的缺陷的计算机实现方法包括将缺陷的一个或多个特征与IL缺陷的一个或多个特征以及非IL缺陷的一个或多个特征进行比较。 该方法还包括将具有基本上与不同组中的IL缺陷和非IL缺陷的一个或多个特征基本一致的一个或多个特性的缺陷合并。

公开(公告)号：US20060084283A1

公开(公告)日：2006-04-20

申请号：US10970317

申请日：2004-10-20

Applicant: Ajit Paranjpe ,  Kangzhan Zhang ,  Brendan McDougall ,  Wayne Vereb ,  Michael Patten ,  Alan Goldman ,  Somnath Nag

Inventor： Ajit Paranjpe ,  Kangzhan Zhang ,  Brendan McDougall ,  Wayne Vereb ,  Michael Patten ,  Alan Goldman ,  Somnath Nag

IPC: H01L21/31

CPC classification number: H01L21/0217 ,  C23C16/345 ,  C23C16/4412 ,  C23C16/45525 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3185

Abstract: A silicon nitride layer is deposited on a substrate within a processing region by introducing a silicon containing precursor into the processing region, exhausting gases in the processing region including the silicon containing precursor while uniformly, gradually reducing a pressure of the processing region, introducing a nitrogen containing precursor into the processing region, and exhausting gases in the processing region including the nitrogen containing precursor while uniformly, gradually reducing a pressure of the processing region. During the steps of exhausting, the slope of the pressure decrease with respect to time is substantially constant.

Abstract translation: 通过将含硅前体引入加工区域，在均匀地引入包含含硅前体的处理区域中的气体中逐渐降低加工区域的压力，引入氮气，在处理区域内的基板上沉积氮化硅层 并且在均匀地排出包含含氮前体的处理区域中的气体，逐渐降低加工区域的压力。 在排气步骤中，压力相对于时间的斜率减小是基本恒定的。

公开(公告)号：US5909628A

公开(公告)日：1999-06-01

申请号：US804484

申请日：1997-02-21

Applicant: Amitava Chatterjee ,  Theodore W. Houston ,  Ih-Chin Chen ,  Agerico L. Esquirel ,  Somnath Nag ,  Iqbal Ali ,  Keith A. Joyner ,  Yin Hu ,  Jeffrey Alan McKee ,  Peter Stewart McAnally

Inventor： Amitava Chatterjee ,  Theodore W. Houston ,  Ih-Chin Chen ,  Agerico L. Esquirel ,  Somnath Nag ,  Iqbal Ali ,  Keith A. Joyner ,  Yin Hu ,  Jeffrey Alan McKee ,  Peter Stewart McAnally

IPC: H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L21/76229 ,  H01L21/31053 ,  Y10S148/05

Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

Abstract translation: 制造半导体器件或集成电路的技术产生平坦化的补充层，其在抛光之后具有比较均匀的厚度，例如通过化学机械抛光（CMP）。 在通常由场氧化物占据的衬底的该部分中的有源区域之间插入虚拟有源区，以便在这些区域中减少在CMP期间发生的“凹陷”。 虚拟有源区域可以采取大块，部分或完全形成的环形结构的形状，或者可以调节其面积密度以匹配衬底的该区域中的有源区的面积密度的多个柱。 支柱的设计规则可以是在多晶硅线或第一级金属化线被放置以避免寄生电容的地方放置柱子。

公开(公告)号：US09401276B2

公开(公告)日：2016-07-26

申请号：US13554103

申请日：2012-07-20

Applicant: Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  David Xuan-Qi Wang ,  Pawan Kapur ,  Somnath Nag ,  George D. Kamian ,  Jay Ashjaee ,  Takao Yonehara

Inventor： Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  David Xuan-Qi Wang ,  Pawan Kapur ,  Somnath Nag ,  George D. Kamian ,  Jay Ashjaee ,  Takao Yonehara

IPC: H01L21/20 ,  H01L31/18

CPC classification number: H01L21/20 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: An apparatus for forming porous silicon layers on at least two surfaces of a plurality of silicon templates in a batch electrochemical anodic etch process is provided. The apparatus comprises a plurality of edge-sealing template mounts operable to prevent formation of porous silicon at the edges of a plurality of templates. An electrolyte is disposed among the plurality of templates. The apparatus further comprises a power supply operable to switch polarity, change current intensity, and control etching time to produce the porous silicon layers.

Abstract translation: 提供了一种在批次电化学阳极蚀刻工艺中在多个硅模板的至少两个表面上形成多孔硅层的装置。 该装置包括多个边缘密封模板安装件，其可操作以防止在多个模板的边缘处形成多孔硅。 在多个模板中设置电解质。 该装置还包括可操作以切换极性，改变电流强度和控制蚀刻时间以产生多孔硅层的电源。

公开(公告)号：US20130171808A1

公开(公告)日：2013-07-04

申请号：US13554103

申请日：2012-07-20

Applicant: Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  David Xuan-Qi Wang ,  Pawan Kapur ,  Somnath Nag ,  George D. Kamian ,  Jay Ashjaee ,  Takao Yonehara

Inventor： Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  David Xuan-Qi Wang ,  Pawan Kapur ,  Somnath Nag ,  George D. Kamian ,  Jay Ashjaee ,  Takao Yonehara

IPC: H01L21/20

CPC classification number: H01L21/20 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.

Abstract translation: 本公开提供了从可再使用的半导体模板的两侧制造TFSS的制造方法和装置设计，从而有效地增加了基板制造的吞吐量并降低了基板的制造成本。 对于给定数量的模板重用周期，这种方法还将每个制造的衬底（TFSS）的平均起始模板成本降低约2倍。

公开(公告)号：US08241940B2

公开(公告)日：2012-08-14

申请号：US13026239

申请日：2011-02-12

Applicant: Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  David Xuan-Qi Wang ,  Pawan Kapur ,  Somnath Nag ,  George D Kamian ,  Jay Ashjaee ,  Takao Yonehara

Inventor： Mehrdad M. Moslehi ,  Karl-Josef Kramer ,  David Xuan-Qi Wang ,  Pawan Kapur ,  Somnath Nag ,  George D Kamian ,  Jay Ashjaee ,  Takao Yonehara

IPC: H01L21/00

CPC classification number: H01L21/20 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.

Abstract translation: 本公开提供了从可再使用的半导体模板的两侧制造TFSS的制造方法和装置设计，从而有效地增加了基板制造的吞吐量并降低了基板的制造成本。 对于给定数量的模板重用周期，这种方法还将每个制造的衬底（TFSS）的平均起始模板成本降低约2倍。

公开(公告)号：US07109097B2

公开(公告)日：2006-09-19

申请号：US11011550

申请日：2004-12-14

Applicant: Ajit Paranjpe ,  Somnath Nag

Inventor： Ajit Paranjpe ,  Somnath Nag

IPC: H01L21/04

CPC classification number: C23C16/045 ,  C23C16/24 ,  H01L21/76232 ,  H01L29/66181

Abstract: A method for void free filling with in-situ doped amorphous silicon of a deep trench structure is provided in which a first fill is carried out in at a temperature, pressure and dopant to silane ratio such that film deposition occurs from the bottom of the trench upwards. By way of this first fill, step coverages well in excess 100% are achieved. In the second fill step, deposition is carried out under changed conditions so as to reduce the impact of dopant on deposition rate, whereby trench fill is completed at a deposition rate which exceeds the deposition rate of the first fill. In an application of this method to the formation of deep trench capacitor structures, the intermediate steps further including the capping of the void free filled trench with a thick layer of amorphous silicon, planarization of the wafer thereafter, followed by a thermal anneal to re-distribute the dopant within the filled trench. Thereafter, additional steps can be performed to complete the formation of the capacitor structure.

Abstract translation: 提供了一种无空隙填充深沟槽结构的原位掺杂非晶硅的方法，其中在硅烷比例的温度，压力和掺杂剂下进行第一次填充，使得从沉积的底部发生膜沉积 向上。 通过这个第一次填充，达到100％以上的步骤覆盖率。 在第二填充步骤中，在改变的条件下进行沉积，以减少掺杂剂对沉积速率的影响，由此以超过第一填充物的沉积速率的沉积速率完成沟槽填充。 在这种方法应用于深沟槽电容器结构的形成中，中间步骤进一步包括无孔填充沟槽的覆盖，其中厚层非晶硅，之后对晶片进行平面化，随后进行热退火， 在填充的沟槽内分布掺杂剂。 此后，可以执行附加步骤以完成电容器结构的形成。

公开(公告)号：US08445314B2

公开(公告)日：2013-05-21

申请号：US12786262

申请日：2010-05-24

Applicant: Suketu Parikh ,  David Dutton ,  Pawan Kapur ,  Somnath Nag ,  Mehrdad Moslehi ,  Joe Kramer ,  Nevran Ozguven ,  Asli Buccu Ucok

Inventor： Suketu Parikh ,  David Dutton ,  Pawan Kapur ,  Somnath Nag ,  Mehrdad Moslehi ,  Joe Kramer ,  Nevran Ozguven ,  Asli Buccu Ucok

IPC: H01L21/00

CPC classification number: H01L29/0692 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02664 ,  H01L31/0236 ,  H01L31/02363 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521 ,  Y10T29/53265

Abstract: A structure and method operable to create a reusable template for detachable thin semiconductor substrates is provided. The template has a shape such that the 3-D shape is substantially retained after each substrate release. Prior art reusable templates may have a tendency to change shape after each subsequent reuse; the present disclosure aims to address this and other deficiencies from the prior art, therefore increasing the reuse life of the template.

Abstract translation: 提供了一种用于为可分离的薄半导体衬底创建可重用模板的结构和方法。 模板具有使得在每个基底释放之后基本保持3-D形状的形状。 现有技术的可再利用模板可能在每次后续重用之后具有改变形状的趋势; 本公开旨在解决现有技术的这种和其他缺陷，因此增加了模板的重用寿命。