公开(公告)号：US20100193925A1

公开(公告)日：2010-08-05

申请号：US12758141

申请日：2010-04-12

Applicant: Tao Cheng

Inventor： Tao Cheng

IPC: H01L23/495

CPC classification number: H05K1/025 ,  G06F17/5077 ,  H01L23/49541 ,  H01L23/64 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19051 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A leadframe for semiconductor packages. The leadframe includes a die pad, a side rail, a tie bar, and a plurality of leads. The side rail is around the die pad. The tie bar connects the die pad and the side rail. The leads extend from the side rail to close proximity to the die pad. Each lead has a corresponding lead relative to a predetermined center line. A predetermined pair of corresponding leads are substantial asymmetrical with each other in appearance relative to the predetermined center line.

Abstract translation: 半导体封装的引线框架。 引线框架包括管芯焊盘，侧轨，连杆和多个引线。 侧轨位于管芯垫周围。 连接杆连接管芯焊盘和侧轨。 引线从侧轨延伸到靠近管芯焊盘。 每个引线相对于预定的中心线具有相应的引线。 相对于预定的中心线，预定的一对对应的引线在外观上彼此大致不对称。

公开(公告)号：US20100156791A1

公开(公告)日：2010-06-24

申请号：US12424708

申请日：2009-04-16

Applicant: Yi-Ping Hsu ,  Tao-Cheng Yen ,  Er-Hao Chen ,  Chung-Hao Yen

Inventor： Yi-Ping Hsu ,  Tao-Cheng Yen ,  Er-Hao Chen ,  Chung-Hao Yen

IPC: G06F3/033

CPC classification number: G06F3/03543 ,  G06F1/3203 ,  G06F1/3231 ,  G06F1/3259 ,  Y02D10/155 ,  Y02D10/173

Abstract: A temperature controlled mouse includes a central controller, a driver control circuit, a temperature control circuit, and a signal transmitting circuit. The driver control circuit generates coordinate control signals and pointer clicking signals, and the signals are transmitted to a host computer coupled to the mouse via the signal transmitting circuit. The temperature control circuit detects the changes of the temperature from a user's hand and thereby generates temperature control signals. The central controller controls the operation status of the mouse according to the temperature control signals, wherein when the temperature detected is within a predetermined temperature range, the central controller wakes the mouse and allows the transmission of signals from the mouse to the host computer; otherwise the central controller stops the transmission of signals. The temperature controlled mouse prevents accidental activation due to negligent bump. Thereby the mouse may only wake from purposeful control and thereby conserves energy.

Abstract translation: 温度控制鼠标包括中央控制器，驱动器控制电路，温度控制电路和信号发送电路。 驱动器控制电路产生坐标控制信号和指针点击信号，并且信号通过信号发送电路发送到耦合到鼠标的主计算机。 温度控制电路检测用户手的温度变化，从而生成温度控制信号。 中央控制器根据温度控制信号控制鼠标的操作状态，其中当检测到的温度在预定温度范围内时，中央控制器唤醒鼠标并允许将信号从鼠标传输到主计算机; 否则中央控制器停止信号的传输。 温度控制的鼠标防止由于疏忽的碰撞引起的意外激活。 因此，鼠标只能从有目的的控制唤醒，从而节约能量。

公开(公告)号：US20100086148A1

公开(公告)日：2010-04-08

申请号：US12571744

申请日：2009-10-01

Applicant: Tien-Chiu HUNG ,  Chung-Shih CHU ,  Tao-Cheng WU

Inventor： Tien-Chiu HUNG ,  Chung-Shih CHU ,  Tao-Cheng WU

IPC: H03G5/00 ,  G10L21/00

CPC classification number: H04R3/04 ,  H03G5/165 ,  H04S7/307

Abstract: An apparatus for processing an audio input signal is provided and includes an audio processing circuit and an audio compressing circuit. The audio processing circuit receives the audio input signal, and enhances a first frequency part of the audio input signal to output a bass-enhancement signal. The audio compressing circuit is coupled to the audio processing circuit, and reduces a gain of a second frequency part of the bass-enhancement signal to output an audio output signal.

Abstract translation: 提供了一种用于处理音频输入信号的装置，并且包括音频处理电路和音频压缩电路。 音频处理电路接收音频输入信号，并且增强音频输入信号的第一频率部分以输出低音增强信号。 音频压缩电路耦合到音频处理电路，并且降低低音增强信号的第二频率部分的增益以输出音频输出信号。

公开(公告)号：US07692968B2

公开(公告)日：2010-04-06

申请号：US11782149

申请日：2007-07-24

Applicant: Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

Inventor： Yao-Wen Chang ,  Guan-Wei Wu ,  Tao-Cheng Lu

IPC: G11C11/34

CPC classification number: G11C16/0466 ,  G11C16/26

Abstract: An operation method of a non-volatile memory is provided. The operation method is that a reading operation is performed to a selected nitride-based memory cell, a first positive voltage is applied to a word line adjacent to one side of the selected memory cell and a second positive voltage is applied to another word line adjacent to the other side of the selected memory cell. The operation method of this present invention not only can reduce a coupling interference issue but also can obtain a wider operation window.

Abstract translation: 提供了一种非易失性存储器的操作方法。 操作方法是对所选择的基于氮化物的存储单元执行读取操作，将第一正电压施加到与所选存储单元的一侧相邻的字线，并且将第二正电压施加到相邻的另一个字线 到所选存储单元的另一侧。 本发明的操作方法不仅可以减少耦合干扰问题，而且可以获得更宽的操作窗口。

公开(公告)号：US20100065943A1

公开(公告)日：2010-03-18

申请号：US12211832

申请日：2008-09-17

Applicant: Tien-Chang Chang ,  Ming-Tzong Yang ,  Tao Cheng ,  Cheng-Hsing Chien ,  Hsin-Hsin Hsiao

Inventor： Tien-Chang Chang ,  Ming-Tzong Yang ,  Tao Cheng ,  Cheng-Hsing Chien ,  Hsin-Hsin Hsiao

IPC: H01L27/04

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0811

Abstract: A method for including decoupling capacitors into a semiconductor circuit having at least a logic circuit therein, includes: arranging a first decoupling capacitor and a second decoupling capacitor into a first area and a second area around the logic circuit respectively, wherein a gate oxide thickness of the first decoupling capacitor is different from a gate oxide thickness of the second decoupling capacitor.

Abstract translation: 一种用于将去耦电容器包括至其中至少具有逻辑电路的半导体电路的方法包括：将第一去耦电容器和第二去耦电容器分别布置在逻辑电路周围的第一区域和第二区域中，其中栅极氧化物厚度 第一去耦电容器与第二去耦电容器的栅极氧化物厚度不同。

公开(公告)号：US20100061026A1

公开(公告)日：2010-03-11

申请号：US12206748

申请日：2008-09-09

Applicant: I-Cheng Lin ,  Tao Cheng

Inventor： I-Cheng Lin ,  Tao Cheng

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H02H3/006

Abstract: An Electrostatic Discharge protection circuit, the circuit includes a transient detecting circuit, a level adjusting circuit, a discharging circuit, and a sustaining circuit. The transient detecting circuit is coupled to a first pad for detecting an input signal at the first pad to generate a transient signal; the level adjusting circuit is coupled to the transient detecting circuit for adjusting an output voltage at an output terminal of the level adjusting circuit; the discharging circuit is coupled to the first pad and the output terminal of the level adjusting circuit for discharging the input signal of the first pad to a second pad when enabled by the output voltage; and the sustaining circuit is coupled between the level adjusting circuit and the transient detecting circuit, for selectively controlling the level adjusting circuit to sustain an enablement of the discharging circuit according to the transient signal.

Abstract translation: 一种静电放电保护电路，电路包括瞬态检测电路，电平调节电路，放电电路和维持电路。 瞬态检测电路耦合到第一焊盘，用于检测第一焊盘处的输入信号以产生瞬态信号; 电平调节电路耦合到瞬态检测电路，用于调整电平调节电路的输出端的输出电压; 放电电路耦合到电平调节电路的第一焊盘和输出端，用于当由输出电压使能时将第一焊盘的输入信号放电到第二焊盘; 并且所述维持电路耦合在所述电平调整电路和所述瞬态检测电路之间，用于选择性地控制所述电平调整电路，以根据所述瞬态信号维持所述放电电路的使能。

公开(公告)号：US07532446B2

公开(公告)日：2009-05-12

申请号：US10838272

申请日：2004-05-05

Applicant: Tao Cheng ,  Hsueh-Kun Liao

Inventor： Tao Cheng ,  Hsueh-Kun Liao

IPC: H02H9/00

CPC classification number: H01L27/0285 ,  H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electro static discharge (ESD) protection circuit employing a field-effect transistor (FET) having no silicide block disposed thereon. It is connected with an internal circuit so as to prevent the internal circuit from the influence of an ESD event, wherein the internal circuit has at least a signal input end. The ESD protection circuit includes: an ESD clamp circuit for providing an ESD grounding path as an ESD occurs; and at least a pair of p-n junction diodes. The p-n junction diodes are stacked so that one of the p-n junction diodes has a n-type end coupled to the signal input end and the other one has a p-type end coupled to the signal input end as well. The ESD clamp circuit has at least a FET, whose drain has no silicide block disposed thereon.

Abstract translation: 采用不设置硅化物块的场效应晶体管（FET）的静电放电（ESD）保护电路。 与内部电路连接，以防止内部电路受到ESD事件的影响，其中内部电路至少具有信号输入端。 ESD保护电路包括：用于提供ESD接地路径作为ESD发生的ESD钳位电路; 和至少一对p-n结二极管。 p-n结二极管被堆叠，使得p-n结二极管中的一个具有耦合到信号输入端的n型端，另一端具有耦合到信号输入端的p型端。 ESD钳位电路至少具有FET，其漏极没有设置在其上的硅化物块。

公开(公告)号：US07529128B2

公开(公告)日：2009-05-05

申请号：US11617613

申请日：2006-12-28

Applicant: Chih Chieh Yeh ,  Wen Jer Tsai ,  Tao Cheng Lu ,  Chih Yuan Lu

Inventor： Chih Chieh Yeh ,  Wen Jer Tsai ,  Tao Cheng Lu ,  Chih Yuan Lu

IPC: G11C11/34

CPC classification number: G11C16/0475 ,  G11C16/10 ,  G11C16/16

Abstract: A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.

Abstract translation: 用于集成电路的存储器架构包括被配置为存储用于一种数据使用模式的数据的第一存储器阵列和被配置为存储用于另一数据使用模式的数据的第二存储器阵列。 第一和第二存储器阵列包括在两个阵列中具有基本上相同结构的基于电荷存储的非易失性存储器单元。 适用于例如数据闪存应用的第一操作算法用于在第一存储器阵列中编程，擦除和读取数据。 适用于例如代码闪存应用的第二操作算法用于在第二存储器阵列中编程，擦除和读取数据，其中第二操作算法与第一操作算法不同。 因此，具有用于代码闪存和数据闪存应用的存储器的一个管芯可以使用简单的工艺以低成本和高产率容易地制造。

公开(公告)号：US20090083262A1

公开(公告)日：2009-03-26

申请号：US12233812

申请日：2008-09-19

Applicant: Kevin Chen-Chuan Chang ,  Tao Cheng ,  Xifeng Yan

Inventor： Kevin Chen-Chuan Chang ,  Tao Cheng ,  Xifeng Yan

IPC: G06F17/30

CPC classification number: G06F17/30867

Abstract: A system has a processor coupled to access a document database that indexes keywords and instances of entities having entity types in a plurality of documents. The processor is programmed to receive an input query including one or more keywords and one or more entity types, and search the database for documents having the keywords and entities with the entity types of the input query. The processor is programmed for aggregating a respective score for each of a plurality of entity tuples across the plurality of documents. The aggregated scores are normalized. Each respective normalized score provides a ranking of a respective entity tuple, relative to other entity tuples, as an answer to the input query. The processor has an interface to a storage or display device or network for outputting a list including a subset of the entity tuples having the highest normalized scores among the plurality of entity tuples.

Abstract translation: 系统具有处理器，其耦合到访问文档数据库，所述文档数据库在多个文档中对具有实体类型的关键字和实体的实例进行索引。 处理器被编程为接收包括一个或多个关键字和一个或多个实体类型的输入查询，并且搜索数据库中具有关键词和具有输入查询的实体类型的实体的文档。 处理器被编程用于聚集跨多个文档的多个实体元组中的每一个的相应分数。 综合得分归一化。 每个相应的归一化分数提供相对于其他实体元组的相应实体元组作为输入查询的答案的排序。 处理器具有到存储或显示设备或网络的接口，用于输出包括多个实体元组中具有最高归一化分数的实体元组的子集的列表。

公开(公告)号：US07348625B2

公开(公告)日：2008-03-25

申请号：US11194545

申请日：2005-08-02

Applicant: Mu-Yi Liu ,  Tao-Cheng Lu

Inventor： Mu-Yi Liu ,  Tao-Cheng Lu

IPC: H01L29/788

CPC classification number: G11C16/0483 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

Abstract: An EEPROM cell includes first and second assist gates on opposite sides of a charge retaining insulating layer. Current in the EEPROM memory cell flows between inversion layers, which are created in response to a bias applied to the assist gates. The insulating layer can include silicon nitride, which is provided between layers of silicon dioxide above the channel region, such that these layers can constitute a dielectric stack, which can be fabricated to occupy a relatively small area.

Abstract translation: EEPROM单元在电荷保持绝缘层的相对侧上包括第一和第二辅助栅极。 在EEPROM存储器单元中的电流在反应层之间流动，反应层响应于施加到辅助栅极的偏置而产生。 绝缘层可以包括氮化硅，其设置在沟道区域上方的二氧化硅层之间，使得这些层可以构成电介质叠层，其可被制造成占据相对小的面积。