公开(公告)号：US20060196526A1

公开(公告)日：2006-09-07

申请号：US11072114

申请日：2005-03-04

Applicant: Jun Wu ,  Dong-Xuan Lu ,  Shih-Chi Lin ,  Wen-Long Lee ,  Yi-An Jian ,  Guang-Cheng Wang ,  Shiu-Ko JangJian ,  Chyi-Tsong Ni ,  Szu-An Wu ,  Ying-Lang Wang

Inventor： Jun Wu ,  Dong-Xuan Lu ,  Shih-Chi Lin ,  Wen-Long Lee ,  Yi-An Jian ,  Guang-Cheng Wang ,  Shiu-Ko JangJian ,  Chyi-Tsong Ni ,  Szu-An Wu ,  Ying-Lang Wang

IPC: C23G1/00 ,  B08B7/00 ,  B08B3/00

CPC classification number: B08B1/04 ,  B08B3/02 ,  H01L21/67051

Abstract: A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

公开(公告)号：US07026233B2

公开(公告)日：2006-04-11

申请号：US10635621

申请日：2003-08-06

Applicant: Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

Inventor： Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

IPC: H01L21/50 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/461

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014

Abstract: A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.

Abstract translation: 公开了一种形成用于集成电路的后钝化互连的方法。 在该集成电路上形成非氧化物材料的钝化层。 然后在钝化层上形成缓冲层。 缓冲层优选是氧化硅层，其厚度基本上小于钝化层的厚度。 在缓冲层上沉积钝化金属层，并且在后钝化金属层中形成连接图案。

公开(公告)号：US20050155625A1

公开(公告)日：2005-07-21

申请号：US10761654

申请日：2004-01-20

Applicant: Shiu-Ko Jangjian ,  Sheng-Wen Chen ,  Hung-Jui Chang ,  Chen-Liang Chang ,  Ying-Lang Wang

Inventor： Shiu-Ko Jangjian ,  Sheng-Wen Chen ,  Hung-Jui Chang ,  Chen-Liang Chang ,  Ying-Lang Wang

IPC: B08B7/00 ,  B08B7/02 ,  B08B9/00 ,  B08B9/08 ,  C23C16/44

CPC classification number: C23C16/4405 ,  B08B7/00

Abstract: A method suitable for cleaning the interior surfaces of a process chamber is disclosed. The invention is particularly effective in removing silicon nitride and silicon dioxide residues from the interior surfaces of a chemical vapor deposition (CVD) chamber. The method includes reacting nitrous oxide (N2O) gas with nitrogen trifluoride (NF3) gas in a plasma to generate nitric oxide (NO) and fluoride (F) radicals. Due to the increased density of nitric oxide radicals generated from the nitrous oxide, the etch and removal rate of the residues on the interior surfaces of the chamber is enhanced. Consequently, the quantity of nitrogen trifluoride necessary to efficiently and expeditiously carry out the chamber cleaning process is reduced.

Abstract translation: 公开了一种适于清洁处理室内表面的方法。 本发明特别有效地从化学气相沉积（CVD）室的内表面去除氮化硅和二氧化硅残余物。 该方法包括在等离子体中使一氧化二氮（N 2 O 2 O）气体与三氟化氮（NF 3 N 3）气体反应以产生一氧化氮（NO）和氟化物（F）基团 。 由于由一氧化二氮产生的一氧化氮自由基的密度增加，腔室内表面上残留物的蚀刻和去除速度增强。 因此，有效且快速地进行室清洁处理所需的三氟化氮的量减少。

公开(公告)号：US20050032353A1

公开(公告)日：2005-02-10

申请号：US10635621

申请日：2003-08-06

Applicant: Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

Inventor： Hsi-Kuei Cheng ,  Hung-Ju Chien ,  Hsun-Chang Chan ,  Chu-Chang Chen ,  Ying-Lang Wang ,  Chin-Hao Su ,  Hsien-Ping Feng ,  Shih-Tzung Chang

IPC: H01L21/4763 ,  H01L21/60 ,  H01L23/31 ,  H01L23/485

CPC classification number: H01L24/13 ,  H01L23/3114 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014

Abstract: A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.

Abstract translation: 公开了一种形成用于集成电路的后钝化互连的方法。 在该集成电路上形成非氧化物材料的钝化层。 然后在钝化层上形成缓冲层。 缓冲层优选是氧化硅层，其厚度基本上小于钝化层的厚度。 在缓冲层上沉积钝化金属层，并且在后钝化金属层中形成连接图案。

公开(公告)号：US06825120B1

公开(公告)日：2004-11-30

申请号：US10176855

申请日：2002-06-21

Applicant: Chi-Wen Liu ,  Ying-Lang Wang

Inventor： Chi-Wen Liu ,  Ying-Lang Wang

IPC: H01L21461

CPC classification number: H01L21/76877 ,  H01L21/7684

Abstract: The present invention relates to a method of protecting a fresh metal surface, preferably copper, after a metal deposition step. The metal deposition is preferably part of single or dual damascene process. The metal surface is treated with an amine, preferably BTA, to form a metal complex that is a hydrophobic monolayer and prevents the underlying metal from reacting to form oxides that can degrade device performance. The amine can be applied in various ways including dipping, spraying, spin coating, and by a CVD method. The sacrificial protective layer can remain on the substrate during a storage period of up to hours or days before it is removed in a subsequent chemical mechanical polish step. The use of a sacrificial protective layer improves throughput in a damascene process by allowing long queue times between metal deposition and CMP which gives more flexibility to production flow and reduces cost.

Abstract translation: 本发明涉及在金属沉积步骤之后保护新鲜金属表面，优选铜的方法。 金属沉积优选是单镶嵌或双镶嵌工艺的一部分。 用胺（优选BTA）处理金属表面以形成作为疏水性单层的金属络合物，并防止下面的金属反应形成可能降低器件性能的氧化物。 胺可以以各种方式施用，包括浸渍，喷涂，旋涂和通过CVD方法。 在后续化学机械抛光步骤中除去之前，牺牲保护层可以在高达数小时或数天的储存期间保留在基材上。 牺牲保护层的使用通过允许金属沉积和CMP之间的长队列时间来提高镶嵌工艺中的生产率，这为生产流程提供了更大的灵活性并降低了成本。

公开(公告)号：US06790778B1

公开(公告)日：2004-09-14

申请号：US10658270

申请日：2003-09-10

Applicant: Yi-Lung Cheng ,  Ying-Lang Wang ,  We-Li Chen

Inventor： Yi-Lung Cheng ,  Ying-Lang Wang ,  We-Li Chen

IPC: H01L2144

CPC classification number: H01L21/76834 ,  H01L21/76883 ,  Y10S438/902 ,  Y10S438/906

Abstract: A method for capping over a copper layer. A copper layer is deposited overlying a substrate. The copper surface is treated with hydrogen-containing plasma to remove copper oxides formed thereon, thereby suppressing copper hillock formation. The treated copper surface is treated again with nitrogen-containing plasma to improve adhesion of the copper surface. A capping layer is formed on the copper layer.

Abstract translation: 一种覆盖铜层的方法。 将铜层沉积在衬底上。 用含氢等离子体处理铜表面以除去其上形成的铜氧化物，从而抑制铜形成小丘。 处理的铜表面再次用含氮等离子体处理以改善铜表面的粘附。 在铜层上形成覆盖层。

公开(公告)号：US06769959B2

公开(公告)日：2004-08-03

申请号：US10050314

申请日：2002-01-15

Applicant: Kei-Wei Chen ,  Ting-Chun Wang ,  Shih-Tzung Chang ,  Yu-Ku Lin ,  Ying-Lang Wang ,  Ming-Wen Chen ,  Kuo-Hsiu Wei

Inventor： Kei-Wei Chen ,  Ting-Chun Wang ,  Shih-Tzung Chang ,  Yu-Ku Lin ,  Ying-Lang Wang ,  Ming-Wen Chen ,  Kuo-Hsiu Wei

IPC: B24B100

CPC classification number: B24B37/04 ,  B24B57/02

Abstract: A method and system is disclosed for reducing slurry usage in a chemical mechanical polishing operation utilizing at least one polishing pad thereof. Slurry can be intermittently supplied to a chemical mechanical polishing device. The slurry is generally flushed so that a portion of said slurry is trapped in a plurality of pores of at least one polishing pad associated with said chemical mechanical polishing device, wherein only a minimum amount of said slurry necessary is utilized to perform said chemical mechanical polishing operation, thereby reducing slurry usage and maintaining a consistent level of slurry removal rate performance and a decrease in particle defects thereof. The present invention thus discloses a method and system for intermittently delivering slurry to a chemical mechanical polishing device in a manner that significantly conserves slurry usage.

Abstract translation: 公开了一种利用其至少一个抛光垫在化学机械抛光操作中减少浆料使用的方法和系统。 浆料可以间歇地供应到化学机械抛光装置。 通常将浆料冲洗，使得所述浆料的一部分被捕获在与所述化学机械抛光装置相关联的至少一个抛光垫的多个孔中，其中仅使用最少量的所需浆料来进行所述化学机械抛光 操作，从而减少浆料的使用并保持一致的浆料去除速率性能水平和其颗粒缺陷的减少。 因此，本发明公开了一种用于以显着节省浆料使用的方式间歇地将浆料输送到化学机械抛光装置的方法和系统。

公开(公告)号：US06673661B1

公开(公告)日：2004-01-06

申请号：US10324965

申请日：2002-12-20

Applicant: Chi-Wen Liu ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Ying-Lang Wang

Inventor： Chi-Wen Liu ,  Ting-Chang Chang ,  Po-Tsun Liu ,  Ying-Lang Wang

IPC: H01L2184

CPC classification number: H01L29/6675 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78684

Abstract: A method for fabricating a dual gate thin film transistor (TFT) device provides for forming a pair of source/drain layers self-aligned with respect to a first gate electrode and forming a second gate electrode self-aligned with respect to both the pair of source/drain layers and the first gate electrode. Thus, the dual gate TFT device is fabricated with enhanced alignment. In addition, the dual gate TFT device (or a single gate TFT device) may be fabricated with source/drain layers formed of a silicon-germanium alloy material, such as to provide the TFT device with enhanced performance with respect to a kink effect.

Abstract translation: 制造双栅极薄膜晶体管（TFT）器件的方法提供了形成相对于第一栅极电极自对准的一对源极/漏极层，并且形成相对于所述一对栅极电极自对准的第二栅电极 源极/漏极层和第一栅极电极。 因此，双栅极TFT器件被制造成具有增强的对准。 此外，双栅极TFT器件（或单栅极TFT器件）可以由硅 - 锗合金材料形成的源极/漏极层制造，以提供相对于扭结效应具有增强性能的TFT器件。

公开(公告)号：US06670274B1

公开(公告)日：2003-12-30

申请号：US10261967

申请日：2002-10-01

Applicant: Chi-Wen Liu ,  Ying-Lang Wang

Inventor： Chi-Wen Liu ,  Ying-Lang Wang

IPC: H01L21302

CPC classification number: H01L21/02068 ,  H01L21/32134 ,  H01L21/76849

Abstract: A method of forming a planarized final copper structure including the following steps. A structure is provided having a patterned dielectric layer formed thereover. The patterned dielectric layer having an opening formed therein. A barrier layer is formed over the patterned dielectric layer, lining the opening. An initial planarized copper structure is formed within the barrier layer lined opening, and is planar with the barrier layer overlying the patterned dielectric layer. The initial planarized copper structure is recessed below the barrier layer overlying the patterned dielectric layer a distance to form a recessed copper structure. Any copper oxide formed upon the recessed copper structure is removed. A conductor film is formed over the recessed, copper oxide-free initial copper structure and the barrier layer. The excess of the conductor film is removed from over the barrier layer, and the excess of the barrier layer overlying the patterned dielectric layer is removed, by a planarization process to form the planarized final copper structure. The planarized final copper structure comprising: the lower, recessed copper oxide-free initial copper structure; and an overlying planarized conductor film, wherein the overlying planarized conductor film isolates the lower, recessed copper oxide-free initial copper structure from the ambient atmosphere.

Abstract translation: 一种形成平面化最终铜结构的方法，包括以下步骤。 提供具有形成在其上的图案化电介质层的结构。 图案化的介电层具有形成在其中的开口。 在图案化的电介质层上形成阻挡层，衬在开口上。 初始的平坦化铜结构形成在阻挡层衬里的开口内，并且与阻挡层叠置在图案化的介电层上是平面的。 初始平坦化的铜结构在阻挡层的下方凹进在图案化的介电层上方一段距离以形成凹陷的铜结构。 形成在凹陷的铜结构上的任何氧化铜被去除。 在凹陷的无铜氧化物的初始铜结构和阻挡层上形成导体膜。 通过平坦化工艺去除覆盖在图案化电介质层上的阻挡层的过量，从而形成平坦化的最终铜结构。 平坦化的最终铜结构包括：较低的凹陷的无铜氧化物的初始铜结构; 和覆盖的平坦化导体膜，其中上覆的平坦化导体膜将较低的凹陷的无铜氧化物的初始铜结构与环境大气隔离。

公开(公告)号：US06585826B2

公开(公告)日：2003-07-01

申请号：US10000891

申请日：2001-11-02

Applicant: Yali Tai ,  Shih-Chi Lin ,  Wen-Long Lee ,  Francis Wang ,  Szu-An Wu ,  Hsi-Kuei Cheng ,  Ying-Lang Wang

Inventor： Yali Tai ,  Shih-Chi Lin ,  Wen-Long Lee ,  Francis Wang ,  Szu-An Wu ,  Hsi-Kuei Cheng ,  Ying-Lang Wang

IPC: C23G102

CPC classification number: H01L21/02063 ,  B08B1/00 ,  B08B3/04 ,  B08B3/12 ,  C11D7/265 ,  C11D11/0047 ,  H01L21/02074 ,  H01L21/67046 ,  H01L21/67057 ,  H01L21/67086 ,  Y10S134/902

Abstract: A method of removing residual contamination including metal nitride particles from semiconductor wafer surfaces including the steps of: providing at least one semiconductor wafer with metal nitride particles adhering to the at least one semiconductor wafer surface thereto; subjecting the at least one semiconductor wafer to at least one mechanical brushing process while a cleaning solution including a carboxylic acid is supplied to at least one semiconductor wafer surface; and, subjecting the at least one semiconductor wafer to an a sonic cleaning process including the carboxylic acid cleaning solution.

Abstract translation: 一种从半导体晶片表面去除包括金属氮化物颗粒的残留污染的方法，包括以下步骤：向至少一个半导体晶片提供附着在至少一个半导体晶片表面上的金属氮化物颗粒; 使至少一个半导体晶片进行至少一个机械刷洗过程，同时将包含羧酸的清洁溶液供应到至少一个半导体晶片表面; 以及对所述至少一个半导体晶片进行包括所述羧酸清洁溶液的声波清洁处理。