公开(公告)号：US06232043B1

公开(公告)日：2001-05-15

申请号：US09318471

申请日：1999-05-25

Applicant: Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

Inventor： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

IPC: G03F700

CPC classification number: B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  H01L21/31053 ,  H01L21/76224

Abstract: A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

Abstract translation: 描述了一种用于计算在CMP期间需要去除的HDP沉积材料的最佳量的简单方法（不引入凹陷）。 该方法来源于我们观察到需要去除的材料的量之间的线性关系以实现完全平坦化，并且称为“用于CMP密度的OD”。 后者被定义为PAx（100-PS），其中PA是相对于总晶片面积的有效面积的百分比，PS是相对于总晶片面积的子区域的百分比。 子区域是在CMP之前被蚀刻出的有源区域之上的电介质区域。 因此，一旦材料被表征，就可以很容易地计算各种不同电路实现的最佳CMP去除厚度。

公开(公告)号：US09419155B2

公开(公告)日：2016-08-16

申请号：US13343922

申请日：2012-01-05

Applicant: Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

Inventor： Shih-Chieh Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC: H01L31/0232 ,  H01L31/101 ,  H01L31/18

CPC classification number: H01L31/0232 ,  H01L31/02327 ,  H01L31/101 ,  H01L31/18

Abstract: This description relates to a sensing product formed using a substrate with a plurality of epi-layers. At least a first epi-layer has a different composition than the composition of a second epi-layer. The sensing product optionally includes at least one radiation sensing element in the second epi-layer and optionally an interconnect structure over the second epi-layer. The sensing product is formed by removing the substrate and all epi-layers other than the second epi-layer. A light incident surface of the second epi-layer has a total thickness variation of less than about 0.15 μm.

Abstract translation: 该描述涉及使用具有多个外延层的基板形成的感测产品。 至少第一外延层具有与第二外延层的组成不同的组成。 感测产品可选地包括第二外延层中的至少一个辐射感测元件以及可选地在第二外延层上的互连结构。 通过去除衬底和除第二外延层之外的所有外延层形成传感产物。 第二外延层的光入射表面具有小于约0.15μm的总厚度变化。

公开(公告)号：US07312149B2

公开(公告)日：2007-12-25

申请号：US10840095

申请日：2004-05-06

Applicant: Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

Inventor： Chao-Lung Chen ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Ying-Lang Wang ,  Yu-Ku Lin ,  Ching-Hwanq Su ,  Po-Jen Shih ,  Shang-Chin Sung

IPC: H01L21/44

CPC classification number: C25D7/123 ,  C25D3/02 ,  C25D5/10 ,  C25D5/18 ,  H01L21/2885

Abstract: A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.

Abstract translation: 在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀 从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。 第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。 低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

公开(公告)号：US06863491B2

公开(公告)日：2005-03-08

申请号：US10339691

申请日：2003-01-08

Applicant: Hsi-Kuei Cheng ,  Chun-Tse Lin ,  Ting-Chun Wang ,  Yu-Ku Lin ,  Ying-Lang Wang

Inventor： Hsi-Kuei Cheng ,  Chun-Tse Lin ,  Ting-Chun Wang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC: H01L21/687 ,  B23B31/16

CPC classification number: H01L21/68707 ,  Y10T279/1033 ,  Y10T279/1291 ,  Y10T279/19

Abstract: A new and improved wafer support for supporting wafers in a process chamber such as an edge bead removal (EBR) chamber. The wafer support comprises multiple wafer support units each including a gripper block that engages an edge portion or bevel of the wafer. The gripper block is attached to an engaging and disengaging mechanism for selectively causing engagement of the gripper blocks with the wafer to support the wafer and disengagement of the gripper blocks from the wafer to release the wafer for removal of the wafer from the chamber. The gripper blocks contact little or none of the surface area on the patterned surface of the wafer to prevent or substantially reduce the formation of contact-induced defects on the wafer.

Abstract translation: 一种新的和改进的晶片支撑件，用于在诸如边缘珠去除（EBR）室的处理室中支撑晶片。 晶片支撑件包括多个晶片支撑单元，每个晶片支撑单元包括接合晶片的边缘部分或斜面的夹持块。 夹持块附接到接合和分离机构，用于选择性地使夹持器块与晶片接合以支撑晶片，并且将夹持器块与晶片分离，以释放晶片以从晶片移除。 夹持器块几乎不接触晶片的图案化表面上的表面积，以防止或基本上减少晶片上接触引起的缺陷的形成。

公开(公告)号：US06514673B2

公开(公告)日：2003-02-04

申请号：US09818962

申请日：2001-03-28

Applicant: Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

Inventor： Hway-Chi Lin ,  Yu-Ku Lin ,  Wen-Pin Chang ,  Ying-Lang Wang

IPC: G03F700

CPC classification number: B24B37/013 ,  B24B37/042 ,  B24B49/12 ,  H01L21/31053 ,  H01L21/76224

Abstract: A simple method for calculating the optimum amount of HDP deposited material that needs to be removed during CMP (without introducing dishing) is described. This method derives from our observation of a linear relationship between the amount of material that needs to be removed in order to achieve full planarization and a quantity called “OD for CMP density”. The latter is defined as PA×(100−PS) where PA is the percentage of active area relative to the total wafer area and PS is the percentage of sub-areas relative to the total wafer area. The sub-areas are regions in the dielectric, above the active areas, that are etched out prior to CMP. Thus, once the materials have been characterized, the optimum CMP removal thickness is readily calculated for a wide range of different circuit implementations.

公开(公告)号：US06352924B1

公开(公告)日：2002-03-05

申请号：US09587463

申请日：2000-06-05

Applicant: Jun Wu ,  Ming Jer Lee ,  Yu Ku Lin ,  Ying-Lang Wang

Inventor： Jun Wu ,  Ming Jer Lee ,  Yu Ku Lin ,  Ying-Lang Wang

IPC: H01L2144

CPC classification number: H01L21/76865 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877

Abstract: A new method is provided to replace tungsten plugs for wafers that trigger the WCVD backside alarm. In this new rework process, the original TiN glue layer is sputter etched back and a new (“fresh”) 100-Angstrom thick layer of TiN is deposited. The new tungsten plug is created over the top surface of the refreshed glue layer.

Abstract translation: 提供了一种新方法来替代触发WCVD背面报警的晶片的钨丝塞。 在这种新的返工过程中，将原始TiN胶层溅射回蚀刻，并沉积出新的（“新鲜”）100埃厚的TiN层。 新的钨丝塞在刷新的胶层的上表面上形成。

公开(公告)号：US6099662A

公开(公告)日：2000-08-08

申请号：US248726

申请日：1999-02-11

Applicant: Ying-Lang Wang ,  Jowei Dun ,  Ken-Shen Chou ,  Yu-Ku Lin

Inventor： Ying-Lang Wang ,  Jowei Dun ,  Ken-Shen Chou ,  Yu-Ku Lin

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  B08B3/00 ,  H01L21/00

CPC classification number: H01L21/02065 ,  H01L21/02074 ,  H01L21/31053 ,  H01L21/3212

Abstract: An improved method for removing residual slurry particles and metallic residues from the surface of a semiconductor substrate after chemical-mechanical polishing has been developed. The cleaning method involves sequential spray cleaning solutions of NH.sub.4 OH and H.sub.2 O, NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, HF and H.sub.2 O, and HCl, H.sub.2 O.sub.2 and H.sub.2 O. The cleaning sequence is: 1. A pre-soak in a spray solution of NH.sub.4 OH and H.sub.2 O; 2. Spray cleaning in a solution of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O; 3. Spray cleaning in a dilute solution of HF and H.sub.2 O; 4. Spray rinsing in DI-water. It is important that slurry particulates first be removed by NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, followed by spray cleaning in a dilute solution of HF and H.sub.2 O to remove metallic residues. The spray cleaning method is superior to brush cleaning methods for both oxide-CMP and tungsten-CMP and results in superior removal of slurry particles and metallic residues introduced by the CMP processes. An optional spray cleaning step using a solution of HCl, H.sub.2 O.sub.2 and H.sub.2 O results in further reduction of metallic residue contamination following oxide-CMP. Compared to traditional brush cleaning the new spray cleaning process has a 2.times. improvement in throughput, less consumption of DI water, and low risk of cross-contamination between sequentially cleaned substrates.

Abstract translation: 已经开发了用于在化学机械抛光之后从半导体衬底的表面除去残余浆料颗粒和金属残留物的改进方法。 清洗方法包括NH 4 OH和H 2 O，NH 4 OH，H 2 O 2和H 2 O，HF和H 2 O以及HCl，H 2 O 2和H 2 O的顺序喷雾清洗溶液。 清洗顺序为：1.在NH4OH和H2O的喷雾溶液中预浸泡; 2.在NH4OH，H2O2和H2O溶液中喷雾清洗; 3.在HF和H2O的稀溶液中喷雾清洗; 4.在DI水中喷淋。 重要的是，首先通过NH 4 OH，H 2 O 2和H 2 O除去浆料颗粒，然后在HF和H 2 O的稀溶液中喷雾清洗以除去金属残余物。 喷雾清洗方法优于氧化物CMP和钨-CMP两者的刷子清洗方法，并且优异地除去由CMP工艺引入的浆料颗粒和金属残留物。 使用HCl，H2O2和H2O溶液的可选喷雾清洗步骤可以进一步降低氧化物CMP后的金属残留污染。 与传统的刷子清洁相比，新的喷雾清洁过程在吞吐量方面有2倍的改善，更少的去离子水消耗，以及顺序清洗的基材之间交叉污染的风险较低。

公开(公告)号：US20070205516A1

公开(公告)日：2007-09-06

申请号：US11364088

申请日：2006-03-01

Applicant: Kei-Wei Chen ,  Sheng-Wen Chen ,  Shiu-Ko Jangjian ,  Shih-Ho Lin ,  Hung-Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

Inventor： Kei-Wei Chen ,  Sheng-Wen Chen ,  Shiu-Ko Jangjian ,  Shih-Ho Lin ,  Hung-Jui Chang ,  Yu-Ku Lin ,  Ying-Lang Wang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/53295 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/0234 ,  H01L21/3121 ,  H01L21/3146 ,  H01L21/31633 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Low-k dielectric layer, semiconductor device, and method for fabricating the same. The low-k dielectric layer comprises a hardened sub-layer sandwiched by two low-k dielectric sub-layers. The hardened sub-layer is formed by a method comprising bombarding the underlying low-k dielectric sub-layer utilizing hydrogen plasma or inert gas plasma. The semiconductor device comprises the low-k dielectric layer overlying an etch stop layer overlying a substrate, and a conductive material embedded in the dielectric layer and the etch stop layer, electrically connecting to the substrate.

Abstract translation: 低k电介质层，半导体器件及其制造方法。 低k电介质层包括夹在两个低k电介质子层之间的硬化子层。 硬化的子层通过利用氢等离子体或惰性气体等离子体轰击下面的低k电介质子层的方法形成。 半导体器件包括覆盖衬底上的蚀刻停止层的低k电介质层，以及电连接到衬底的埋入电介质层和蚀刻停止层中的导电材料。

公开(公告)号：US06769959B2

公开(公告)日：2004-08-03

申请号：US10050314

申请日：2002-01-15

Applicant: Kei-Wei Chen ,  Ting-Chun Wang ,  Shih-Tzung Chang ,  Yu-Ku Lin ,  Ying-Lang Wang ,  Ming-Wen Chen ,  Kuo-Hsiu Wei

Inventor： Kei-Wei Chen ,  Ting-Chun Wang ,  Shih-Tzung Chang ,  Yu-Ku Lin ,  Ying-Lang Wang ,  Ming-Wen Chen ,  Kuo-Hsiu Wei

IPC: B24B100

CPC classification number: B24B37/04 ,  B24B57/02

Abstract: A method and system is disclosed for reducing slurry usage in a chemical mechanical polishing operation utilizing at least one polishing pad thereof. Slurry can be intermittently supplied to a chemical mechanical polishing device. The slurry is generally flushed so that a portion of said slurry is trapped in a plurality of pores of at least one polishing pad associated with said chemical mechanical polishing device, wherein only a minimum amount of said slurry necessary is utilized to perform said chemical mechanical polishing operation, thereby reducing slurry usage and maintaining a consistent level of slurry removal rate performance and a decrease in particle defects thereof. The present invention thus discloses a method and system for intermittently delivering slurry to a chemical mechanical polishing device in a manner that significantly conserves slurry usage.

Abstract translation: 公开了一种利用其至少一个抛光垫在化学机械抛光操作中减少浆料使用的方法和系统。 浆料可以间歇地供应到化学机械抛光装置。 通常将浆料冲洗，使得所述浆料的一部分被捕获在与所述化学机械抛光装置相关联的至少一个抛光垫的多个孔中，其中仅使用最少量的所需浆料来进行所述化学机械抛光 操作，从而减少浆料的使用并保持一致的浆料去除速率性能水平和其颗粒缺陷的减少。 因此，本发明公开了一种用于以显着节省浆料使用的方式间歇地将浆料输送到化学机械抛光装置的方法和系统。

公开(公告)号：US06551927B1

公开(公告)日：2003-04-22

申请号：US09880920

申请日：2001-06-15

Applicant: Dian-Hau Chen ,  Kwang-Ming Lin ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Jin-Kuen Lan

Inventor： Dian-Hau Chen ,  Kwang-Ming Lin ,  Yu-Ku Lin ,  Tong-Hua Kuan ,  Jin-Kuen Lan

IPC: H01L2144

CPC classification number: H01L29/665 ,  H01L21/28518

Abstract: A cobalt silicide process having a titanium-rich/titanium nitride capping layer to improve junction leakage is described. Semiconductor device structures to be silicided are formed in and on a semiconductor substrate. A cobalt layer is deposited overlying the semiconductor device structures. A titanium-rich/titanium nitride capping layer is deposited overlying the cobalt layer. Thereafter, a cobalt silicide layer is formed on the semiconductor device structures. The titanium-rich/titanium nitride capping layer and an unreacted portion of the cobalt layer are removed to complete fabrication of the integrated circuit device.

Abstract translation: 描述了具有富钛/氮化钛覆盖层以改善结漏电的硅化钴工艺。 半导体衬底上形成硅化硅半导体器件结构。 覆盖在半导体器件结构上的钴层被沉积。 覆盖在钴层上的富钛/氮化钛覆盖层被沉积。 此后，在半导体器件结构上形成钴硅化物层。 除去富钛/氮化钛覆盖层和钴层的未反应部分以完成集成电路器件的制造。