公开(公告)号：US20220121616A1

公开(公告)日：2022-04-21

申请号：US17561917

申请日：2021-12-24

Applicant: Altera Corporation

Inventor： Chee Hak Teh ,  Arifur Rahman

IPC: G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F1/06 ,  G06F1/10

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2x clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US20210103534A1

公开(公告)日：2021-04-08

申请号：US16933628

申请日：2020-07-20

Applicant: ALTERA CORPORATION

Inventor： Arifur Rahman ,  Bernhard Friebe

IPC: G06F13/16 ,  H03K19/003 ,  H03K19/173 ,  G11C7/22 ,  G06F13/40 ,  G06F13/42 ,  G11C8/00 ,  G11C29/12 ,  H01L23/538 ,  H01L25/18 ,  H03K19/1776

Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

公开(公告)号：US20200073851A1

公开(公告)日：2020-03-05

申请号：US16674138

申请日：2019-11-05

Applicant: Altera Corporation

Inventor： Chee Hak Teh ,  Arifur Rahman

IPC: G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F1/06 ,  G06F1/10

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US20190303317A1

公开(公告)日：2019-10-03

申请号：US16378356

申请日：2019-04-08

Applicant: ALTERA CORPORATION

Inventor： Arifur Rahman ,  Bernhard Friebe

IPC: G06F13/16 ,  H01L23/538 ,  G11C7/22 ,  H03K19/177 ,  G06F13/40 ,  G11C8/00 ,  G06F13/42 ,  H01L25/18 ,  H03K19/003 ,  H03K19/173 ,  G11C29/12

Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

公开(公告)号：US09935052B1

公开(公告)日：2018-04-03

申请号：US14554667

申请日：2014-11-26

Applicant: Altera Corporation

Inventor： Hui Liu ,  Karthik Chandrasekar ,  Kyung Suk Oh ,  Kaushik Chanda ,  Arifur Rahman

IPC: H05K1/11 ,  H05K1/14 ,  H01L23/528 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/5286 ,  H01L23/481 ,  H01L23/5385 ,  H01L24/14 ,  H01L2224/1403

Abstract: Circuitry having power lines with comparable path resistances may include input-output blocks in an integrated circuit (IC) that are coupled to respective sets of bumps on the IC. The circuitry may have a core region and a periphery region. Groups of input-output blocks may be formed in the periphery region. A first set of power lines in the circuitry extends from the core region to the first group of input-output blocks whereas a second set of power lines in the circuitry extends from the core region to the second group of input-output blocks. The first and second sets of power lines are physically separate from each other.

公开(公告)号：US20160163609A1

公开(公告)日：2016-06-09

申请号：US14805312

申请日：2015-07-21

Applicant: Altera Corporation

Inventor： Arifur Rahman ,  Chee Hak Teh

IPC: H01L21/66 ,  G01R31/28 ,  H01L25/065

CPC classification number: H01L22/32 ,  G01R31/2856 ,  G01R31/2889 ,  G01R31/2896 ,  G01R31/3172 ,  G01R31/318513 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Ways for testing a multichip package while reducing the required test pin count are provided. The multichip package may include a main die coupled to multiple daughter components. During testing, one of the daughter components may be selected for testing while other daughter components sit idle. The daughter components may receive test signals via a shared path. Dedicated select pins may be used to activate the selected daughter component while placing the unselected components in tristate mode. The selection of daughter components during testing can also be controlled directly using the main die. If desired, general-purpose input-output (GPIO) pins of the main die may be borrowed from the main die to convey the test signals to the selected daughter component during testing. If desired, multiplexing circuitry may also be used to selectively route signals to the daughter components during testing.

Abstract translation: 提供了测试多芯片封装同时减少所需测试引脚数量的方法。 多芯片封装可以包括耦合到多个子部件的主管芯。 在测试期间，可以选择其中一个子组件进行测试，而其他子组件闲置。 子组件可以经由共享路径接收测试信号。 专用选择引脚可用于激活所选择的子组件，同时将未选择的组件置于三态模式。 在测试期间选择子组件也可以使用主模具直接控制。 如果需要，主芯片的通用输入输出（GPIO）引脚可以从主管芯借用，以便在测试期间将测试信号传送到所选择的子元件。 如果需要，复用电路也可用于在测试期间选择性地将信号路由到子组件。

公开(公告)号：US11194757B2

公开(公告)日：2021-12-07

申请号：US17037642

申请日：2020-09-29

Applicant: Altera Corporation

Inventor： Chee Hak Teh ,  Arifur Rahman

IPC: G06F15/78 ,  G06F13/00 ,  G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F1/06 ,  G06F1/10

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US20170206176A1

公开(公告)日：2017-07-20

申请号：US15422310

申请日：2017-02-01

Applicant: ALTERA CORPORATION

Inventor： Arifur Rahman ,  Bernhard Friebe

IPC: G06F13/16 ,  G06F13/42 ,  G11C29/12 ,  H01L23/538 ,  H03K19/177 ,  H03K19/173 ,  H01L25/18 ,  G06F13/40 ,  G11C8/00

CPC classification number: G06F13/1689 ,  G06F1/00 ,  G06F13/4068 ,  G06F13/42 ,  G11C7/22 ,  G11C8/00 ,  G11C29/12 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H03K19/00 ,  H03K19/003 ,  H03K19/1733 ,  H03K19/1776

Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

公开(公告)号：US20170133329A1

公开(公告)日：2017-05-11

申请号：US15412535

申请日：2017-01-23

Applicant: Altera Corporation

Inventor： Arifur Rahman ,  Karthik Chandrasekar

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  G06F17/50

CPC classification number: H01L23/562 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/40 ,  G06F2217/78 ,  G06F2217/80 ,  G06F2217/82 ,  G06F2217/84 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/16 ,  H01L27/0688 ,  H01L2224/16227 ,  H03K19/177

Abstract: A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. A method is provided for optimizing the design of the electronic package by choosing the appropriate number of metallization layers to be added to the interposer.

公开(公告)号：US09583431B1

公开(公告)日：2017-02-28

申请号：US14538646

申请日：2014-11-11

Applicant: Altera Corporation

Inventor： Arifur Rahman ,  Karthik Chandrasekar

IPC: H01L23/522 ,  H01L27/06 ,  G06F17/50 ,  H01L23/528

CPC classification number: H01L23/562 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/06 ,  G06F2217/08 ,  G06F2217/40 ,  G06F2217/78 ,  G06F2217/80 ,  G06F2217/82 ,  G06F2217/84 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/16 ,  H01L27/0688 ,  H01L2224/16227 ,  H03K19/177

Abstract: A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce warpage, the interconnection array of the integrated circuit does not include a thick metallization layer; and at least part of the power distribution function that would otherwise have been performed by the thick metallization layer is performed by one or more metallization layers that are added to the interposer. A method is provided for optimizing the design of the electronic package by choosing the appropriate number of metallization layers to be added to the interposer.

Abstract translation: 提供了一种2.5D电子封装件，其中至少一个集成电路安装在安装在封装基板上的插入器上。 为了减少翘曲，集成电路的互连阵列不包括厚的金属化层; 并且另外由厚金属化层执行的功率分配功能的至少一部分由添加到插入器的一个或多个金属化层进行。 提供了一种通过选择要添加到插入器的适当数量的金属化层来优化电子封装的设计的方法。