公开(公告)号：US11281605B2

公开(公告)日：2022-03-22

申请号：US16933628

申请日：2020-07-20

Applicant: ALTERA CORPORATION

Inventor： Arifur Rahman ,  Bernhard Friebe

IPC: G06F13/16 ,  H03K19/003 ,  H03K19/173 ,  G11C7/22 ,  G06F13/40 ,  G06F13/42 ,  G11C29/12 ,  H01L25/18 ,  H03K19/1776 ,  G11C8/00 ,  H01L23/538 ,  G06F1/00 ,  H03K19/00 ,  H01L23/00 ,  H01L25/065

Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

公开(公告)号：US11226925B2

公开(公告)日：2022-01-18

申请号：US16674138

申请日：2019-11-05

Applicant: Altera Corporation

Inventor： Chee Hak Teh ,  Arifur Rahman

IPC: G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  G06F13/00 ,  G06F1/06 ,  G06F1/10

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US20210011878A1

公开(公告)日：2021-01-14

申请号：US17037642

申请日：2020-09-29

Applicant: Altera Corporation

Inventor： Chee Hak Teh ,  Arifur Rahman

IPC: G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F1/06 ,  G06F1/10

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US20200226094A1

公开(公告)日：2020-07-16

申请号：US16833068

申请日：2020-03-27

Applicant: Altera Corporation

Inventor： Chee Hak Teh ,  Arifur Rahman

IPC: G06F15/78 ,  G06F13/42 ,  G06F13/40 ,  G06F1/06 ,  G06F1/10

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US10482060B2

公开(公告)日：2019-11-19

申请号：US15954078

申请日：2018-04-16

Applicant: Altera Corporation

Inventor： Chee Hak Teh ,  Arifur Rahman

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/38 ,  G06F15/78 ,  G06F13/42 ,  G06F1/06 ,  G06F1/10

Abstract: A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.

公开(公告)号：US10296474B2

公开(公告)日：2019-05-21

申请号：US15422310

申请日：2017-02-01

Applicant: ALTERA CORPORATION

Inventor： Arifur Rahman ,  Bernhard Friebe

IPC: H03K19/177 ,  H03K19/173 ,  H01L23/538 ,  G11C29/12 ,  G06F13/16 ,  G06F13/42 ,  H03K19/003 ,  G11C7/22 ,  G06F13/40 ,  G11C8/00 ,  H01L25/18 ,  G06F1/00 ,  H03K19/00 ,  H01L23/00 ,  H01L25/065

Abstract: Systems and methods are provided to enhance the functionality of an integrated circuit. Such an integrated circuit may include a primary circuitry and an embedded programmable logic programmable to adjust the functionality of the primary circuitry. Specifically, the embedded programmable logic may be programmed to adjust the functionality of the primary circuitry to complement and/or support the functionality of another integrated circuit. Accordingly, the embedded programmable logic may be programmed with functions such as data/address manipulation functions, configuration/testing functions, computational functions, or the like.

公开(公告)号：US10082541B2

公开(公告)日：2018-09-25

申请号：US14737246

申请日：2015-06-11

Applicant: Altera Corporation

Inventor： Dana How ,  Dinesh Patil ,  Arifur Rahman ,  Jeffrey Erik Schulz

IPC: G06F13/00 ,  G06F13/20 ,  G06F3/00 ,  G01R31/3185 ,  G01R31/28 ,  H01L25/065 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F11/00

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

公开(公告)号：US20160363626A1

公开(公告)日：2016-12-15

申请号：US14737246

申请日：2015-06-11

Applicant: Altera Corporation

Inventor： Dana How ,  Dinesh Patil ,  Arifur Rahman ,  Jeffrey Erik Schulz

IPC: G01R31/3185 ,  G01R31/28 ,  H01L25/065

CPC classification number: G01R31/318597 ,  G01R31/2896 ,  G06F11/00 ,  G06F11/1625 ,  G06F11/186 ,  G06F11/2007 ,  H01L25/0652 ,  H01L2225/06527

Abstract: Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

Abstract translation: 提供了具有多个集成电路管芯的集成电路封装。 多芯片封装可以包括通过晶片间封装互连耦合到一个或多个从裸片的主裸片。 可以实施混合（即，主动和被动）互连冗余方案以帮助修复潜在的故障互连以提高组装产量。 携带正常用户信号的互连可以使用主动冗余方案通过在必要时选择性地切换到使用备用驱动器块来修复。 另一方面，可以使用无源冗余方案来支持携带上电复位信号，初始化信号和用于同步主器件和从器件之间的操作的其他关键控制信号的互连，通过使用两个或更多个复制线来为每个 关键信号。

公开(公告)号：US09331062B1

公开(公告)日：2016-05-03

申请号：US14099792

申请日：2013-12-06

Applicant: Altera Corporation

Inventor： Christopher F. Lane ,  Arifur Rahman

IPC: H01L23/52 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L21/76801 ,  H01L23/481 ,  H01L23/5286 ,  H01L23/642 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L27/0629 ,  H01L27/0694 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Integrated circuits with backside power delivery capabilities are provided. An integrated circuit may include a substrate having front and back surfaces, a first interconnect stack formed on the front surface, and a second interconnect stack formed on the back surface. Routing structures that carry data signals, control signals, and other user signals may be formed only in the first interconnect stack. A large majority of routing structures that carry power supply signals may be formed in the second interconnect stack. Decoupling capacitor circuitry such as deep trench capacitors may be formed in the back surface of the substrate. The integrated circuit may be mounted on a package substrate. The first interconnect stack may be coupled to the package substrate via wire bond pads, whereas the second interconnect stack may be coupled to the package substrate via an array of solder bumps.

Abstract translation: 提供具有背面功率输送功能的集成电路。 集成电路可以包括具有前表面和后表面的基板，形成在前表面上的第一互连叠层和形成在背面上的第二互连叠层。 携带数据信号，控制信号和其他用户信号的路由结构可以仅在第一互连栈中形成。 携带电源信号的绝大多数路由结构可以形成在第二互连堆栈中。 去耦电容器电路如深沟槽电容器可以形成在衬底的背面。 集成电路可以安装在封装衬底上。 第一互连堆叠可以经由引线接合焊盘耦合到封装衬底，而第二互连堆叠可以经由焊料凸块的阵列耦合到封装衬底。

公开(公告)号：US08866304B2

公开(公告)日：2014-10-21

申请号：US13725591

申请日：2012-12-21

Applicant: Altera Corporation

Inventor： Arifur Rahman ,  Wai-Bor Leung

IPC: H01L23/48 ,  H01L23/538 ,  H05K1/11 ,  H01L21/78

CPC classification number: H01L23/5384 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81

Abstract: Systems, methods, and devices are provided to enable an integrated circuit device of relatively higher capacity. Such an integrated circuit device may include at least two component integrated circuits that communicate with one another. Specifically, the component integrated circuits may communicate through a “stitched silicon interposer” that is larger than a reticle limit of the lithography system used to manufacture the interposer. To achieve this larger size, the stitched silicon interposer may be composed of at least two component interposers, each sized within the reticle limit and each separated from one another by a die seal structure.

Abstract translation: 提供了系统，方法和设备以使得具有相对更高容量的集成电路器件。 这种集成电路装置可以包括彼此通信的至少两个组件集成电路。 具体地，组件集成电路可以通过比用于制造插值器的光刻系统的掩模版极限大的“缝合硅插入器”进行通信。 为了实现这种更大的尺寸，缝合硅插入件可以由至少两个分量插入件组成，每个分量插入件尺寸在标线极限内并且通过模具密封结构彼此分离。