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    Reducing latency in a peripheral component interconnect express link
    21.
    发明授权
    Reducing latency in a peripheral component interconnect express link 有权
    减少外设组件互连中的延迟快速链接

    公开(公告)号：US09015396B2

    公开(公告)日：2015-04-21

    申请号：US13622266

    申请日：2012-09-18

    Applicant: Apple Inc.

    Inventor： Michael W. Murphy ,  Joshua P. de Cesare ,  Timothy R. Paaske

    IPC: G06F13/24 ,  G06F1/32 ,  G06F1/00

    CPC classification number: G06F13/24 ,  G06F1/3253 ,  Y02D10/151

    Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.

    Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。

    SYSTEM POWER MANAGEMENT USING COMMUNICATION BUS PROTOCOLS
    22.
    发明申请
    SYSTEM POWER MANAGEMENT USING COMMUNICATION BUS PROTOCOLS 有权
    使用通信总线协议的系统电源管理

    公开(公告)号：US20150089259A1

    公开(公告)日：2015-03-26

    申请号：US14032335

    申请日：2013-09-20

    Applicant: Apple Inc.

    Inventor： David S. Warren ,  Inna Levit ,  Timothy R. Paaske

    IPC: G06F1/32 ,  G06F1/08

    CPC classification number: G06F1/3296 ,  G06F1/06 ,  G06F1/08 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/325 ,  G06F13/4022 ,  G06F13/4282 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

    Abstract: Embodiments of an apparatus and method are disclosed that may allow for managing power of a computing system. The apparatus may include a clock generation circuit, a bus interface unit, and a control circuit. The clock generation circuit may be configured to generate multiple clock signals. Each clock signal may provide a timing reference to different functional blocks within a device coupled to the communication bus. The bus interface unit may be configured to receive messages from the device via the communication bus. The messages may include a latency value and a request to activate a low power mode. The control circuit may be configured to deactivate one or more of the multiple clock signals dependent upon the latency value and multiple threshold values.

    Abstract translation: 公开了可以允许管理计算系统的功率的装置和方法的实施例。 该装置可以包括时钟发生电路，总线接口单元和控制电路。 时钟发生电路可以被配置为产生多个时钟信号。 每个时钟信号可以提供与耦合到通信总线的设备内的不同功能块的定时参考。 总线接口单元可以被配置为经由通信总线从设备接收消息。 消息可以包括延迟值和激活低功率模式的请求。 控制电路可以被配置为取决于等待时间值和多个阈值的多个时钟信号中的一个或多个。

    AUTHENTICATION AND CONTROL OF ENCRYPTION KEYS
    25.
    发明申请
    AUTHENTICATION AND CONTROL OF ENCRYPTION KEYS 审中-公开

    公开(公告)号：US20200342091A1

    公开(公告)日：2020-10-29

    申请号：US16927934

    申请日：2020-07-13

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Weihua Mao ,  Shu-Yi Yu

    IPC: G06F21/46 ,  G06F21/60 ,  G06F21/44 ,  G06F21/85 ,  H04L9/08

    Abstract: An apparatus, a method, and a system are presented in which the apparatus includes an interface control circuit that may be configured to receive a message including a cryptographic keyword and a policy value. The policy value may include one or more data bits indicative of one or more policies that define allowable usage of the cryptographic keyword. The apparatus also includes a security circuit that may be configured to extract the cryptographic keyword and the policy value from the message, and to apply at least one policy of the one or more policies to usage of the cryptographic keyword in response to a determination that an authentication of the message succeeded.

    SOFTWARE FAULT MONITORING
    26.
    发明申请
    SOFTWARE FAULT MONITORING 审中-公开

    公开(公告)号：US20200081785A1

    公开(公告)日：2020-03-12

    申请号：US16129726

    申请日：2018-09-12

    Applicant: Apple Inc.

    Inventor： Zhimin Chen ,  Timothy R. Paaske ,  Yannick L. Sierra ,  Anish C. Trivedi

    IPC: G06F11/14 ,  G06F11/30 ,  G06F11/34

    Abstract: A method for verifying program flow during execution of a software program in a computer system is disclosed. Program code of the software program includes multiple program instructions and checkpoint data structures, where a given checkpoint data structure is associated with a given program instruction and is linked to at least one other checkpoint data structure. A fault monitor circuit may receive a particular checkpoint data structure and compare the particular checkpoint data structure to a previously received checkpoint data structure that is associated with another program instruction. Based on results of the comparison, the software fault monitor circuit may signal a program flow error.

    Secure public key acceleration
    27.
    发明授权
    Secure public key acceleration 有权

    公开(公告)号：US10521596B1

    公开(公告)日：2019-12-31

    申请号：US16138670

    申请日：2018-09-21

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Mitchell D. Adler ,  Conrad Sauerwald ,  Fabrice L. Gautier ,  Shu-Yi Yu

    IPC: G06F21/60 ,  G06F21/62

    Abstract: In an embodiment, a system is provided in which the private key is managed in hardware and is not visible to software. The system may provide hardware support for public key generation, digital signature generation, encryption/decryption, and large random prime number generation without revealing the private key to software. The private key may thus be more secure than software-based versions. In an embodiment, the private key and the hardware that has access to the private key may be integrated onto the same semiconductor substrate as an integrated circuit (e.g. a system on a chip (SOC)). The private key may not be available outside of the integrated circuit, and thus a nefarious third party faces high hurdles in attempting to obtain the private key.

    Systems and methods for detecting replay attacks on security space
    28.
    发明授权
    Systems and methods for detecting replay attacks on security space 有权

    公开(公告)号：US10243990B1

    公开(公告)日：2019-03-26

    申请号：US15275044

    申请日：2016-09-23

    Applicant: Apple Inc.

    Inventor： Zhimin Chen ,  Timothy R. Paaske ,  Gilbert H. Herbeck

    IPC: G06F21/64 ,  H04L29/06 ,  G06F21/60

    Abstract: A system and method for detecting replay attacks on secure data are disclosed. A system on a chip (SOC) includes a security processor. Blocks of data corresponding to sensitive information are stored in off-chip memory. The security processor uses an integrity data structure, such as an integrity tree, for the blocks. The intermediate nodes of the integrity tree use nonces which have been generated independent of any value within a corresponding block. By using only the nonces to generate tags in the root at the top layer stored in on-chip memory and the nodes of the intermediate layers stored in off-chip memory, an amount of storage used is reduced for supporting the integrity tree. When the security processor detects events which create access requests for one or more blocks, the security processor uses the integrity tree to verify a replay attack has not occurred and corrupted data.

    Secure public key acceleration
    30.
    发明授权
    Secure public key acceleration 有权

    公开(公告)号：US10114956B1

    公开(公告)日：2018-10-30

    申请号：US15860314

    申请日：2018-01-02

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Mitchell D. Adler ,  Conrad Sauerwald ,  Fabrice L. Gautier ,  Shu-Yi Yu

    IPC: G06F21/60 ,  G06F21/62

    Abstract: In an embodiment, a system is provided in which the private key is managed in hardware and is not visible to software. The system may provide hardware support for public key generation, digital signature generation, encryption/decryption, and large random prime number generation without revealing the private key to software. The private key may thus be more secure than software-based versions. In an embodiment, the private key and the hardware that has access to the private key may be integrated onto the same semiconductor substrate as an integrated circuit (e.g. a system on a chip (SOC)). The private key may not be available outside of the integrated circuit, and thus a nefarious third party faces high hurdles in attempting to obtain the private key.

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