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    LATCH BIT CELLS
    22.
    发明申请
    LATCH BIT CELLS 有权

    公开(公告)号：US20220359015A1

    公开(公告)日：2022-11-10

    申请号：US17359209

    申请日：2021-06-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Russell J. Schreiber ,  John J. Wuu

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C16/08 ,  G11C7/10

    Abstract: A bit cell of an SRAM implemented using standard cell design rules includes a write portion and a read portion. The write portion includes a pass gate coupled to an input node of the bit cell and supplies data on the input node to a first node of the bit cell while write word line signals are asserted. An inverter is coupled to the first node and supplies inverted data. A keeper circuit that is coupled to the inverter maintains the data on the first node when the write word line signals are deasserted. The read portion of the bit cell receives read word line signals and the inverted data and is responsive to assertion of the read word line signals to supply an output node of the read portion of the bit cell with output data that corresponds to the data on the first node.

    SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS
    24.
    发明申请
    SCHEME FOR ENABLING DIE REUSE IN 3D STACKED PRODUCTS 有权

    公开(公告)号：US20210098441A1

    公开(公告)日：2021-04-01

    申请号：US16586309

    申请日：2019-09-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John J. Wuu ,  Milind S. Bhagavat ,  Brett P. Wilkerson ,  Rahul Agarwal

    IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00

    Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.

    MEMORY INCLUDING SIDE-CAR ARRAYS WITH IRREGULAR SIZED ENTRIES
    26.
    发明申请
    MEMORY INCLUDING SIDE-CAR ARRAYS WITH IRREGULAR SIZED ENTRIES 审中-公开

    公开(公告)号：US20180210994A1

    公开(公告)日：2018-07-26

    申请号：US15416731

    申请日：2017-01-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： John J. Wuu ,  Patrick J. Shyvers ,  Ryan Alan Selby

    IPC: G06F17/50 ,  G11C7/06 ,  G11C7/20

    CPC classification number: G06F17/5077 ,  G06F17/5072 ,  G06F17/5081 ,  G11C5/025 ,  G11C7/06 ,  G11C7/20

    Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. A memory macro block includes at least a primary array and a sidecar array. The primary array stores a first portion of a memory line and the sidecar array stores a second smaller portion of the memory line being accessed. The primary array and the sidecar array have different heights. The height of the sidecar array is based on a notch height in at least one corner of the memory macro block. The notch creates on-die space for s reserved area on the die. The notches result in cross-shaped, T-shaped, and/or L-shaped memory macro blocks.

    SRAM power savings and write assist
    27.
    发明授权
    SRAM power savings and write assist 有权

    公开(公告)号：US12165700B2

    公开(公告)日：2024-12-10

    申请号：US17488519

    申请日：2021-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Russell J. Schreiber ,  John J. Wuu ,  Keith A. Kasprak

    IPC: G11C11/419 ,  G11C11/418

    Abstract: A technique reduces power consumption of a bit cell in a memory and provides write assistance to the bit cell. When the bit cell is active, a power-saving write-assist circuit coupled to the bit cell is selectively sized according to a type of memory access. When the bit cell is inactive, the virtual power supply node floats to a predetermined voltage between a first voltage on a first power supply node coupled to the bit cell and a second voltage on a second power supply node coupled to the bit cell. A method for controlling power consumption of a bit cell and assisting a write to the bit cell includes providing a reference voltage to a virtual power supply node coupled to the bit cell. The reference voltage is provided based on an operational state of the bit cell and a type of memory access to the bit cell.

    Dual read port latch array bitcell
    28.
    发明授权
    Dual read port latch array bitcell 有权

    公开(公告)号：US12073919B2

    公开(公告)日：2024-08-27

    申请号：US17359445

    申请日：2021-06-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

    IPC: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    CPC classification number: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on an opposed edge from the single write bit line. The layout uses a dummy gate placed over both p-type diffusion and n-type diffusion between the edges. The layout has a same number of p-type transistors as n-type transistors despite using asymmetrical read access circuits. The layout also has a contacted gate pitch that is one more than the number of p-type transistors.

    Split read port latch array bit cell
    29.
    发明授权
    Split read port latch array bit cell 有权

    公开(公告)号：US12033721B2

    公开(公告)日：2024-07-09

    申请号：US17359446

    申请日：2021-06-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

    IPC: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    CPC classification number: G11C8/16 ,  G06F30/392 ,  G11C11/418 ,  G11C11/419

    Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.

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