公开(公告)号：US20200161743A1

公开(公告)日：2020-05-21

申请号：US16197352

申请日：2018-11-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01Q1/22 ,  H01Q9/04 ,  H01Q21/06 ,  H01L23/66 ,  H01Q23/00 ,  H01Q21/00 ,  H01L23/00

Abstract: An antenna package includes a patterned antenna structure and an encapsulant. The patterned antenna structure includes a first surface, a second surface opposite the first surface and a third surface extended between the first surface and the second surface. The encapsulant is disposed on the first surface of the patterned antenna structure. The third surface of the patterned antenna structure includes a first portion covered by the encapsulant and a second portion exposed from the encapsulant.

公开(公告)号：US20200027810A1

公开(公告)日：2020-01-23

申请号：US16038037

申请日：2018-07-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/373 ,  H01L23/00

Abstract: The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.

公开(公告)号：US20190252305A1

公开(公告)日：2019-08-15

申请号：US15893180

申请日：2018-02-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-Shu PENG ,  Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16235

Abstract: A substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer and comprising an interconnection structure, and an interconnection element. The interconnection element extends from the first surface of the first dielectric layer to the second surface of the first dielectric layer and is surrounded by the interconnection structure.

公开(公告)号：US20180145017A1

公开(公告)日：2018-05-24

申请号：US15356407

申请日：2016-11-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan TSAI ,  Po-Shu PENG ,  Cheng-Lin HO ,  Chih Cheng LEE

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

Abstract: A semiconductor substrate includes a multi-layered structure, a component and a first conductive via. The multi-layered structure includes a plurality of dielectric layers and a plurality of patterned conductive layers. A topmost patterned conductive layer of the patterned conductive layers is embedded in a topmost dielectric layer of the dielectric layers. The component is embedded in the multi-layered structure. The first conductive via is electrically connected to the component and one of the patterned conductive layers. At least one of the patterned conductive layers is located at a depth spanning between a top surface of the passive layer and a bottom surface of the component

公开(公告)号：US20180130759A1

公开(公告)日：2018-05-10

申请号：US15348899

申请日：2016-11-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE ,  Li-Chuan TSAI

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.

公开(公告)号：US20180005846A1

公开(公告)日：2018-01-04

申请号：US15630847

申请日：2017-06-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan TSAI ,  Chih-Cheng LEE ,  Cheng-Lin HO

IPC: H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/498 ,  H01L24/16

Abstract: A substrate includes a dielectric layer having a first surface and a second surface opposite to the first surface, a first circuit layer and at least one second conductive element. The first circuit layer is disposed adjacent to the first surface of the dielectric layer, and includes at least one trace and at least one first conductive element connected to the trace. The first conductive element does not extend through the dielectric layer. The second conductive element extends through the dielectric layer. An area of an upper surface of the second conductive element is substantially equal to an area of an upper surface of the first conductive element.