公开(公告)号：US20170019993A1

公开(公告)日：2017-01-19

申请号：US14798384

申请日：2015-07-13

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H05K3/00 ,  H05K3/22 ,  H05K1/02 ,  H05K3/36

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

Abstract translation: 本公开涉及半导体衬底，半导体模块及其制造方法。 半导体衬底包括第一电介质结构，第二电介质结构，第一图案化导电层和第二图案化导电层。 第一电介质结构具有与第一表面相对的第一表面和第二表面。 第二电介质结构具有与第三表面相对的第三表面和第四表面，其中第四表面与第一表面相邻。 第二电介质结构限定了从第三表面延伸到第四表面的通孔。 空腔由通孔和第一电介质结构限定。 第一图案化导电层设置在第一电介质结构的第一表面上。 第二图案化导电层设置在第一介电结构的第二表面上。

公开(公告)号：US20160150651A1

公开(公告)日：2016-05-26

申请号：US14550615

申请日：2014-11-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H01L21/48 ,  H01L23/498

CPC classification number: H05K1/186 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K3/007 ,  H05K3/34 ,  H05K2203/06 ,  H01L2924/00

Abstract: The present disclosure relates to a semiconductor device substrate and a method for making the same. The semiconductor device substrate includes a first dielectric layer, a second dielectric layer and an electronic component. The first dielectric layer includes a body portion, and a wall portion protruded from a first surface of the body portion. The wall portion has an end. The second dielectric layer has a first surface and an opposing second surface. The first surface of the second dielectric layer is adjacent to the first surface of the body portion. The second dielectric layer surrounds the wall portion. The end of the wall portion extends beyond the second surface of the second dielectric layer. The electronic component includes a first electrical contact and a second electrical contact. At least a part of the electronic component is surrounded by the wall portion.

Abstract translation: 本公开涉及一种半导体器件基板及其制造方法。 半导体器件基板包括第一介电层，第二介电层和电子部件。 第一电介质层包括主体部分和从主体部分的第一表面突出的壁部分。 壁部分有一端。 第二电介质层具有第一表面和相对的第二表面。 第二电介质层的第一表面与主体部分的第一表面相邻。 第二电介质层围绕壁部。 壁部分的端部延伸超过第二介电层的第二表面。 电子部件包括第一电接触和第二电接触。 电子部件的至少一部分被壁部包围。

公开(公告)号：US20160240462A1

公开(公告)日：2016-08-18

申请号：US14624388

申请日：2015-02-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu CHEN ,  Kuang-Hsiung CHEN ,  Sheng-Ming WANG ,  Yu-Ying LEE ,  Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure, a dielectric structure and a metal bump. The conductive structure has a first conductive surface and a second conductive surface. The dielectric structure has a first dielectric surface and a second dielectric surface. The first conductive surface does not protrude from the first dielectric surface. The second conductive surface is recessed from the second dielectric surface. The metal bump is disposed in a dielectric opening of the dielectric structure, and is physically and electrically connected to the second conductive surface. The metal bump has a concave surface.

Abstract translation: 本公开涉及一种半导体衬底结构，半导体封装及其制造方法。 半导体衬底结构包括导电结构，电介质结构和金属凸块。 导电结构具有第一导电表面和第二导电表面。 电介质结构具有第一电介质表面和第二电介质表面。 第一导电表面不从第一电介质表面突出。 第二导电表面从第二电介质表面凹陷。 金属凸块设置在电介质结构的电介质开口中，并且物理地和电连接到第二导电表面。 金属凸块具有凹面。

公开(公告)号：US20200258826A1

公开(公告)日：2020-08-13

申请号：US16859676

申请日：2020-04-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE ,  Li-Chuan TSAI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/16 ,  H01L21/683

Abstract: A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.

公开(公告)号：US20180033719A1

公开(公告)日：2018-02-01

申请号：US15725144

申请日：2017-10-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/02 ,  H05K3/36 ,  H05K3/22 ,  H05K3/00 ,  H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: (1) a first dielectric structure having a first surface and a second surface opposite the first surface; (2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; (3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and (4) a second patterned conductive layer, disposed on and contacting the second surface of the first dielectric structure and including at least one conductive trace, wherein the first dielectric structure defines at least one opening, and a periphery of the opening corresponds to a periphery of the through hole of the second dielectric structure.

公开(公告)号：US20200006315A1

公开(公告)日：2020-01-02

申请号：US16020953

申请日：2018-06-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Wu Chang WANG

IPC: H01L27/02 ,  H01L21/67 ,  H01L21/66 ,  H01L23/544 ,  H01L21/78 ,  H01L21/56

Abstract: A substrate structure includes at least one detachable first substrate unit and a substrate body. The detachable first substrate unit includes a plurality of corners and a plurality of first engagement portions. Each of the first engagement portions is disposed at each of the corners of the detachable first substrate unit. The substrate body includes a plurality of second substrate units, at least one opening and a plurality of second engagement portions. The opening is substantially defined by a plurality of sidewalls of the second substrate units, and includes a plurality of corners. Each of the second engagement portions is disposed at each of the corners of the opening. The detachable first substrate unit is disposed in the opening, and the second engagement portions are engaged with the first engagement portions.

公开(公告)号：US20180130759A1

公开(公告)日：2018-05-10

申请号：US15348899

申请日：2016-11-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE ,  Li-Chuan TSAI

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.

公开(公告)号：US20170077023A1

公开(公告)日：2017-03-16

申请号：US15364143

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

Abstract translation: 半导体衬底包括：1）具有第一表面和与第一表面相对的第二表面的第一电介质结构; 2）具有与第三表面相对的第三表面和第四表面的第二介电结构，其中第四表面面向第一表面，第二介电结构限定从第三表面延伸到第四表面的通孔，其中腔是 由通孔和第一电介质结构限定; 3）设置在第一介电结构的第一表面上的第一图案化导电层; 以及4）第二图案化导电层，设置在所述第一介电结构的第二表面上并且包括至少一个导电迹线。 第一介电结构限定至少一个开口以暴露第二图案化导电层的一部分。