公开(公告)号：US10152565B2

公开(公告)日：2018-12-11

申请号：US14730082

申请日：2015-06-03

Applicant: Altera Corporation

Inventor： Benjamin Gamsa ,  Gordon Raymond Chiu

IPC: G06F17/50

Abstract: Circuit design computing equipment may perform register retiming operations to improve the performance of a circuit design after having performed placement and routing operations. For example, the circuit design computing equipment may perform register retiming operations that move registers from a first portion of a circuit design that operates in a first clock domain into a synchronization region that separates the first portion of the circuit design from a second portion of the circuit design that operates in a second clock domain that is different than the first clock domain. Performing register retiming operations that move registers into a synchronization region between clock domains may solve the so-called short path—long path problem in which a long path that would benefit from a register retiming operation is coupled in parallel to a short path that has no location to receive a register during the register retiming operation.

公开(公告)号：US09679633B2

公开(公告)日：2017-06-13

申请号：US14997268

申请日：2016-01-15

Applicant: Altera Corporation

Inventor： Krzysztof Maryan ,  Gordon Raymond Chiu ,  Warren Nordyke ,  Navid Azizi

IPC: G11C11/4076 ,  G11C7/10 ,  G11C8/18 ,  G06F1/12 ,  G11C11/4093 ,  G11C29/02

CPC classification number: G11C11/4076 ,  G06F1/12 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4093 ,  G11C29/023

Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

公开(公告)号：US09552456B2

公开(公告)日：2017-01-24

申请号：US14726237

申请日：2015-05-29

Applicant: Altera Corporation

Inventor： Gordon Raymond Chiu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5054 ,  G06F17/5077 ,  G06F2217/14 ,  G06F2217/84

Abstract: A circuit design may have registers and combinational gates. Circuit design computing equipment may perform register retiming in the circuit design, whereby registers are moved across combinational gates. Information about the register moves may be recorded, and a modified circuit design is created. The circuit design computing equipment may implement the circuit design in an integrated circuit. A logic analyzer may be used to debug the circuit design implemented in the integrated circuit in real-time and at high-speed. To facilitate the debugging process, the circuit design computing equipment may augment the integrated circuit and/or compensate for register retiming based on the information recorded during register retiming.

Abstract translation: 电路设计可以具有寄存器和组合门。 电路设计计算设备可以在电路设计中执行寄存器重新定时，由此寄存器在组合门上移动。 可以记录关于寄存器移动的信息，并且创建修改的电路设计。 电路设计计算设备可以在集成电路中实现电路设计。 可以使用逻辑分析器来实时和高速地对集成电路中实现的电路设计进行调试。 为了便于调试过程，电路设计计算设备可以基于在寄存器重新定时期间记录的信息来增加集成电路和/或补偿寄存器重新定时。

公开(公告)号：US09384311B1

公开(公告)日：2016-07-05

申请号：US14341030

申请日：2014-07-25

Applicant: Altera Corporation

Inventor： Nishanth Sinnadurai ,  Gordon Raymond Chiu

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5054 ,  G06F2217/84

Abstract: A method of configuring an integrated circuit device with a user logic design includes placing and routing the user logic design, retiming the placed and routed user logic design, examining the retimed user logic design for at least one path that lacks sufficient registers for retiming, and rerouting the user logic design to find additional registers for further retiming the at least one path. Portions of the method may be performed iteratively until a condition, which may be a performance criterion, is met. The method may further include assuming the paths that are constrained have been repaired, and examining further paths downstream from those paths.

Abstract translation: 配置具有用户逻辑设计的集成电路设备的方法包括放置和布线用户逻辑设计，重新定位放置和路由的用户逻辑设计，检查针对至少一个缺少足够的重新定时寄存器的路径的重定时用户逻辑设计，以及 重新路由用户逻辑设计以找到用于进一步重新定时至少一个路径的附加寄存器。 可以迭代地执行该方法的一部分，直到满足可能是性能标准的条件为止。 该方法还可以包括假设被修复的路径已经被修复，并且检查从这些路径下游的更多路径。

公开(公告)号：US09275184B1

公开(公告)日：2016-03-01

申请号：US14159905

申请日：2014-01-21

Applicant: Altera Corporation

Inventor： Gordon Raymond Chiu

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/84

Abstract: A method for designing a system on a target device includes performing register retiming on the system. A critical chain in the system is detected, wherein the critical chain includes a plurality of register-to-register paths and where improving timing on one of the register-to-register paths improves timing on other register-to-register paths. Properties of the critical chain are reported.

Abstract translation: 用于在目标设备上设计系统的方法包括在系统上执行注册重新定时。 检测到系统中的关键链，其中关键链包括多个寄存器到寄存器路径，并且其中一个寄存器到寄存器路径上的改善定时改善了其他寄存器到寄存器路径上的定时。 报告关键链的性质。

公开(公告)号：US09195793B1

公开(公告)日：2015-11-24

申请号：US14154623

申请日：2014-01-14

Applicant: Altera Corporation

Inventor： Mark Stephen Wheeler ,  Gordon Raymond Chiu

IPC: G06F9/45 ,  G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/84

Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.

Abstract translation: 用于在目标设备上设计系统的方法包括为系统生成解决方案。 保留由用户识别的系统的模块的解决方案。 用于模块的保存的解决方案在由用户识别的目标设备上的位置实现。

公开(公告)号：US08929152B1

公开(公告)日：2015-01-06

申请号：US14243102

申请日：2014-04-02

Applicant: Altera Corporation

Inventor： Benjamin Gamsa ,  Gordon Raymond Chiu

IPC: G11C16/04 ,  G11C7/20

CPC classification number: G11C7/20 ,  G06F17/5054 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/22 ,  H03K19/1776

Abstract: A method of retiming a circuit that includes a RAM having data stored therein, a register following the RAM, and registers preceding the RAM for registering input, address and enable signals of the RAM includes pushing a value in the register following the RAM back into a memory location in the RAM, pushing back data stored in the RAM and initial values in the registers preceding the RAM to accommodate the value pushed back from the register following the RAM, and setting new values in the registers preceding the RAM so that, on a first clock cycle after retiming, the circuit assumes a condition before retiming. The method also may be used to configure a programmable logic device with a user logic design.

Abstract translation: 一种对包括其中存储有数据的RAM的电路重新定时的方法，RAM之后的寄存器以及用于登记RAM的输入，地址和使能信号的RAM之前的寄存器，包括将RAM后的寄存器中的值推回到 RAM中的存储器位置，推回存储在RAM中的数据和RAM前的寄存器中的初始值，以适应从RAM之后的寄存器推回的值，并在RAM之前的寄存器中设置新值，以便在 重新定时后的第一个时钟周期，该电路在重新定时之前假设一个条件。 该方法还可用于配置具有用户逻辑设计的可编程逻辑器件。

公开(公告)号：US20140269117A1

公开(公告)日：2014-09-18

申请号：US13829881

申请日：2013-03-14

Applicant: Altera Corporation

Inventor： Krzysztof Maryan ,  Gordon Raymond Chiu ,  Warren Nordyke ,  Navid Azizi

IPC: G11C8/18

CPC classification number: G11C11/4076 ,  G06F1/12 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/18 ,  G11C11/4093 ,  G11C29/023

Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

Abstract translation: 一方面，一种方法包括：接收包括第一和第二分量的差分选通信号; 由第一缓冲器缓冲第一和第二组分; 以及通过第二缓冲器缓冲所述第一组件。 该方法包括由控制逻辑块接收第二缓冲器的输出。 该方法包括在第一和第二分量的值处于第一逻辑状态但在差分选通信号中接收到脉冲串脉冲之前的时间段之后，从第一逻辑状态检测第一分量中的转变 到第二逻辑状态，并且响应于检测到的转换，确定使能信号。 该方法还包括通过选通逻辑块接收使能信号和第一缓冲器的输出，并且当使能信号被断言时，对第一缓冲器的输出进行非门控。

公开(公告)号：US10394997B2

公开(公告)日：2019-08-27

申请号：US16134770

申请日：2018-09-18

Applicant: Altera Corporation

Inventor： Mark Stephen Wheeler ,  Gordon Raymond Chiu

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes generating a solution for the system. A solution for a module of the system identified by a user is preserved. The preserved solution for the module is implemented at a location on the target device identified by the user.

公开(公告)号：US10339238B2

公开(公告)日：2019-07-02

申请号：US15626089

申请日：2017-06-17

Applicant: Altera Corporation

Inventor： Salem Derisavi ,  Gordon Raymond Chiu ,  Benjamin Gamsa

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.