公开(公告)号：US10339244B1

公开(公告)日：2019-07-02

申请号：US14595375

申请日：2015-01-13

Applicant: Altera Corporation

Inventor： Benjamin Gamsa ,  Gordon Raymond Chiu

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes performing speculative register retiming with speculative changes made to a design of the system after an initial compilation of the design. A strategy is generated for an actual register retiming in response to user specified preferences on the speculative changes.

公开(公告)号：US09489480B1

公开(公告)日：2016-11-08

申请号：US14295752

申请日：2014-06-04

Applicant: Altera Corporation

Inventor： Gordon Raymond Chiu ,  Benjamin Gamsa ,  Paul Mark Leventis

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5022 ,  G06F17/505

Abstract: Techniques for compiling an integrated circuit (IC) design with an electronic design automation (EDA) tool are provided. The IC design may be compiled for different IC devices. When the IC design is compiled for a selected integrated circuit device, the EDA tool may analyze the IC design to determine whether the design is compatible with the selected IC device. If the IC design contains elements that are incompatible with the selected IC device, the EDA tool may compile the design based on a simulated removal of the incompatible elements. In some instances, the EDA tool may identify optimization opportunities in the IC design and may compile the design based on an optimized version of the IC design. The EDA tool may generate a compilation output (e.g., a performance analysis report) based on the simulated removal of the incompatible elements (or the optimized version of the IC design.

Abstract translation: 提供了使用电子设计自动化（EDA）工具编译集成电路（IC）设计的技术。 IC设计可以针对不同的IC器件进行编译。 当为所选择的集成电路器件编译IC设计时，EDA工具可以分析IC设计，以确定设计是否与选定的IC器件兼容。 如果IC设计包含与所选IC器​​件不兼容的元件，则EDA工具可以基于模拟删除不兼容元素来编译设计。 在某些情况下，EDA工具可以识别IC设计中的优化机会，并且可以基于IC设计的优化版本来编译设计。 EDA工具可以基于不兼容元件（或IC设计的优化版本）的模拟移除来生成编译输出（例如，性能分析报告）。

公开(公告)号：US10671781B2

公开(公告)日：2020-06-02

申请号：US15951127

申请日：2018-04-11

Applicant: Altera Corporation

Inventor： Salem Derisavi ,  Gordon Raymond Chiu ,  Benjamin Gamsa ,  David Ian M. Milton

IPC: G06F30/30 ,  G06F30/3312 ,  G06F30/327 ,  G06F30/398 ,  G06F119/12

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.

公开(公告)号：US20160357899A1

公开(公告)日：2016-12-08

申请号：US14730082

申请日：2015-06-03

Applicant: Altera Corporation

Inventor： Benjamin Gamsa ,  Gordon Raymond Chiu

IPC: G06F17/50

CPC classification number: G06F17/5054 ,  G06F17/505 ,  G06F2217/84

Abstract: Circuit design computing equipment may perform register retiming operations to improve the performance of a circuit design after having performed placement and routing operations. For example, the circuit design computing equipment may perform register retiming operations that move registers from a first portion of a circuit design that operates in a first clock domain into a synchronization region that separates the first portion of the circuit design from a second portion of the circuit design that operates in a second clock domain that is different than the first clock domain. Performing register retiming operations that move registers into a synchronization region between clock domains may solve the so-called short path—long path problem in which a long path that would benefit from a register retiming operation is coupled in parallel to a short path that has no location to receive a register during the register retiming operation.

Abstract translation: 电路设计计算设备可以执行寄存器重新定时操作，以在执行放置和布线操作之后改善电路设计的性能。 例如，电路设计计算设备可以执行寄存器重定时操作，其将寄存器从在第一时钟域中操作的电路设计的第一部分移动到将电路设计的第一部分与电路设计的第二部分分开的同步区域 电路设计在与第一时钟域不同的第二时钟域中工作。 将寄存器迁移到时钟域之间的同步区域的执行寄存器重新定时操作可以解决所谓的短路径长路径问题，其中将从寄存器重定时操作中受益的长路径并行耦合到没有 在寄存器重新定时操作期间接收寄存器的位置。

公开(公告)号：US09251876B1

公开(公告)日：2016-02-02

申请号：US14560153

申请日：2014-12-04

Applicant: Altera Corporation

Inventor： Benjamin Gamsa ,  Gordon Raymond Chiu

IPC: G11C7/00 ,  G11C7/20 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/20 ,  G06F17/5054 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/22 ,  H03K19/1776

Abstract: A method of retiming a circuit that includes a RAM having data stored therein, a register following the RAM, and registers preceding the RAM for registering input, address and enable signals of the RAM includes pushing a value in the register following the RAM back into a memory location in the RAM, pushing back data stored in the RAM and initial values in the registers preceding the RAM to accommodate the value pushed back from the register following the RAM, and setting new values in the registers preceding the RAM so that, on a first clock cycle after retiming, the circuit assumes a condition before retiming. The method also may be used to configure a programmable logic device with a user logic design.

公开(公告)号：US10339238B2

公开(公告)日：2019-07-02

申请号：US15626089

申请日：2017-06-17

Applicant: Altera Corporation

Inventor： Salem Derisavi ,  Gordon Raymond Chiu ,  Benjamin Gamsa

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.

公开(公告)号：US09971858B1

公开(公告)日：2018-05-15

申请号：US14627220

申请日：2015-02-20

Applicant: Altera Corporation

Inventor： Salem Derisavi ,  Gordon Raymond Chiu ,  Benjamin Gamsa ,  David Ian M. Milton

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5081 ,  G06F2217/84

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.

公开(公告)号：US20170286590A1

公开(公告)日：2017-10-05

申请号：US15626089

申请日：2017-06-17

Applicant: Altera Corporation

Inventor： Salem Derisavi ,  Gordon Raymond Chiu ,  Benjamin Gamsa

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5027 ,  G06F17/505 ,  G06F2217/84

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.

公开(公告)号：US09710591B1

公开(公告)日：2017-07-18

申请号：US14627191

申请日：2015-02-20

Applicant: Altera Corporation

Inventor： Salem Derisavi ,  Gordon Raymond Chiu ,  Benjamin Gamsa

IPC: G06F17/50

CPC classification number: G06F17/5031 ,  G06F17/5027 ,  G06F17/505 ,  G06F2217/84

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Constraints are generated that prevent registers residing in the area from being used for register retiming.

公开(公告)号：US10586004B2

公开(公告)日：2020-03-10

申请号：US14746237

申请日：2015-06-22

Applicant: Altera Corporation

Inventor： Nishanth Sinnadurai ,  Benjamin Gamsa

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes performing one of synthesis, placement, and routing on the system. A designer is presented with a timing analysis of the system after one of the synthesis, placement, and routing, wherein the timing analysis reflects register retiming optimizations predicted to be implemented on the system. One of the synthesis, placement, and routing is modified in response to input provided by the designer after the presenting.