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公开(公告)号：US10122269B2
公开(公告)日：2018-11-06
申请号：US15402827
申请日：2017-01-10
Applicant: Apple Inc.
Inventor： Fabio Gozzini , Jay B. Fletcher , Shawn Searles , Sanjay Pant
Abstract: A system that includes a regulator circuit is disclosed. The regulator circuit includes first and second phase units whose outputs are coupled to a power supply node of a circuit block, via respective coupled inductors. The first phase unit may initiate a charge cycle of the power supply node in response to assertion of a clock signal and generate a compensated current using currents measure through both inductors and the clock signal. In response to a determination that the compensated current is greater than a demand current generated using a voltage level of the power supply node and a reference voltage, the first phase unit may halt the charge cycle.
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公开(公告)号：US20180083534A1
公开(公告)日：2018-03-22
申请号：US15403255
申请日：2017-01-11
Applicant: Apple Inc.
Inventor： Sanjay Pant , Fabio Gozzini , Jay B. Fletcher , Shawn Searles
CPC classification number: H02M3/158 , H02M1/08 , H02M3/1584 , H02M2001/0009 , H02M2003/1586
Abstract: A system that includes a regulator unit is disclosed. The regulator unit includes first and second phase units whose outputs are coupled to through first and second coupled inductors, respectively, to a power supply node of a circuit block. The first phase unit may be configured to discharge, for a first period of time, the power supply node through the first inductor in response to determining a sense current is greater than a demand current. The operation of the second phase unit may follow that of the first phase unit after a second period of time has elapsed.
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公开(公告)号：US09503068B1
公开(公告)日：2016-11-22
申请号：US15068003
申请日：2016-03-11
Applicant: Apple Inc.
Inventor： Joseph T. DiBene, II , Sanjay Pant , Sotirios Zogopoulos , Jafar Savoj , Inder M. Sodhi
Abstract: In an embodiment, a supply voltage envelope detector circuit is configured to detect a shape of the supply voltage over time and to compare the detected shape to expected shapes that indicate voltage droop events for which corrective action may be needed. The expected shapes may be predetermined based on one or more of: the design of the integrated circuit that includes the supply voltage envelope detector circuit; attributes of the power management unit (PMU) that is to generate the supply voltage for the integrated circuit; and/or attributes of the system that includes the integrated circuit. The shape of the voltage droop may experience little variation during use, and thus may be used to detect a droop event earlier and more accurately than a threshold-based mechanism, in some embodiments.
Abstract translation: 在一个实施例中，电源电压包络检测器电路被配置为随时间检测电源电压的形状，并将检测到的形状与指示可能需要校正动作的电压下降事件的预期形状进行比较。 预期形状可以基于以下中的一个或多个来预先确定：包括电源电压包络检测器电路的集成电路的设计; 用于生成集成电路的电源电压的电源管理单元（PMU）的属性; 和/或包括集成电路的系统的属性。 在一些实施例中，电压下降的形状可能在使用期间几乎没有变化，因此可以用于比基于阈值的机制更早和更准确地检测下垂事件。
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公开(公告)号：US20240396452A1
公开(公告)日：2024-11-28
申请号：US18792905
申请日：2024-08-02
Applicant: Apple Inc.
Inventor： Jay B. Fletcher , Nathan F. Hanagami , Sanjay Pant , Hao Zhou , Shawn Searles
Abstract: A voltage regulator circuit included in a computer system may employ a control circuit and a switch array that includes multiple switch circuits. Different groups of switch circuits that include respective groups of switch devices are coupled between an input power supply node and corresponding regulated power supply nodes. To maintain desired respective voltages on the regulated power supply nodes, the control circuit compares the voltages of the regulated power supply nodes to corresponding reference voltages and, based on results of the comparisons, opens and closes various ones of the switch devices included in the different groups of switch circuits.
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公开(公告)号：US20240241571A1
公开(公告)日：2024-07-18
申请号：US18622502
申请日：2024-03-29
Applicant: Apple Inc.
Inventor： Shawn Searles , Sanjay Pant , Ludmil N. Nikolov , Tiago Filipe Galhoz Patrao , Enrico Zanetti , Hao Zhou , Vincenzo Bisogno
IPC: G06F1/3296 , H02M1/00 , H02M3/157
CPC classification number: G06F1/3296 , H02M1/0006 , H02M1/0025 , H02M1/007 , H02M3/157
Abstract: A power delivery system included in a computer system uses multiple power converter circuits to generate respective voltage levels on multiple power supply nodes. An embodiment of the power delivery system includes an input power converter circuit that generates a voltage level for use by host and follower power converter circuits. The host power converter circuit generates an external demand current that is shared by multiple follower power converter circuits to regulate the voltage level on the multiple power supply nodes. The power delivery system can be scaled to different platforms of the computer system by adjusting the number of follower power converter circuits.
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Patent Agency Ranking
公开(公告)号：US11983063B2
公开(公告)日：2024-05-14
申请号：US17823949
申请日：2022-08-31
Applicant: Apple Inc.
Inventor： Shawn Searles , Sanjay Pant , Ludmil N. Nikolov , Tiago Filipe Galhoz Patrao , Enrico Zanetti , Hao Zhou , Vincenzo Bisogno
IPC: G06F1/32 , G06F1/3296 , H02M1/00 , H02M3/157
CPC classification number: G06F1/3296 , H02M1/0006 , H02M1/0025 , H02M1/007 , H02M3/157
Abstract: A power delivery system included in a computer system using multiple power converter circuits to generate respective voltage levels on multiple power supply nodes. The power delivery system includes a step-down power converter circuit that generates a voltage level for use by host and follower power converter circuits. The host power converter circuit generates an external demand current that is shared by multiple follower power converter circuits to regulate the voltage level on the multiple power supply nodes. The power delivery system can be scaled to different platforms of the computer system by adjusting the number of follower power converter circuits.
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公开(公告)号：US20240126353A1
公开(公告)日：2024-04-18
申请号：US18497443
申请日：2023-10-30
Applicant: Apple Inc.
Inventor： Shawn Searles , Fabio Gozzini , Sanjay Pant , Inder M. Sodhi
CPC classification number: G06F1/26 , G01R15/146 , G11C7/1096
Abstract: A power converter circuit included in a computer system may include a phase circuit and a sample circuit. The phase circuit compares a voltage level of the regulated power supply node to a reference voltage to generate a demand current that is used to adjust the voltage level of the regulated power supply node. The phase circuit also digitizes the demand current and stores the resultant bit stream in a memory circuit. The sample circuit generates timestamp information that points to particular storage locations in the memory circuit that correspond to trigger events, allowing the operation of the power converter circuit to be analyzed during different circumstances as well as to adjust operating parameters of the power converter circuit.
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公开(公告)号：US20240014739A1
公开(公告)日：2024-01-11
申请号：US18474677
申请日：2023-09-26
Applicant: Apple Inc.
Inventor： Sanjay Pant , Fabio Gozzini , Hubert Attah , Jonathan F. Bolus , Wenxun Huang , Koushik Vaithyanathan , Alberto Puggelli
IPC: H02M3/158 , H02M3/157 , G06F1/3203 , H03M1/12
CPC classification number: H02M3/1584 , H02M3/157 , G06F1/3203 , H03M1/12 , H02M3/1586
Abstract: A power converter with slew rate detection is disclosed. A power converter comprises a plurality of phase circuits coupled to a regulated power supply line via corresponding ones of a plurality of inductors. A first control loop generates, using digital samples and based on comparisons of a reference voltage to a voltage on the regulated power supply line, a first plurality of control signals. A second control loop, using the digital samples, generates a second plurality of control signals based on a rate of change of the voltage of the regulated power supply line. The second control loop causes the first control loop to control the plurality of phase circuits in response to detecting that the rate of change is within a specified range, and causes the second control loop to control the plurality of phase circuits, in response to detecting that the rate of change exceeds the specified range.
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公开(公告)号：US11431249B2
公开(公告)日：2022-08-30
申请号：US17005129
申请日：2020-08-27
Applicant: Apple Inc.
Inventor： Alberto Alessandro Angelo Puggelli , Ofir Gilad , Floyd L. Dankert , Hubert Attah , Sanjay Pant , Shawn Searles , Georg Diebel
Abstract: A power converter circuit that includes a switch node coupled to a regulated power supply node via an inductor is configured to regulate a voltage level of a power supply node using a particular one of multiple available operating modes. In response to receiving a command to reduce the voltage level of the power supply node, the power converter circuit begins to reduce the voltage level of the power supply node, while autonomously selecting different ones of available operating modes. The power converter circuit may compare to the voltage level of the power supply node to boundary levels and select a different operating mode when the voltage level of the power supply node exceeds one of the boundaries. By switching operating modes during the negative slew of the voltage level of the power supply node, the power converter may maintain a target efficiency during the reduction in voltage.
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公开(公告)号：US10924124B2
公开(公告)日：2021-02-16
申请号：US16851821
申请日：2020-04-17
Applicant: Apple Inc.
Inventor： Brian S. Leibowitz , Jared L. Zerbe , Sanjay Pant
Abstract: Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency.
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