公开(公告)号：US09583339B2

公开(公告)日：2017-02-28

申请号：US15091916

申请日：2016-04-06

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  CNRS Centre National de la Recherche Scientifique ,  APPLIED MATERIALS, Inc.

Inventor： Nicolas Posseme ,  Thibaut David ,  Olivier Joubert ,  Thorsten Lill ,  Srinivas Nemani ,  Laurent Vallier

IPC: H01L21/302 ,  H01L21/02 ,  H01L21/306 ,  H01L21/265 ,  H01L21/3065

CPC classification number: H01L21/0234 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66628 ,  H01L29/66772

Abstract: A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.

Abstract translation: 提供一种用于形成场效应晶体管的栅极的间隔物的方法，栅极位于半导体材料层之上，包括形成覆盖栅极的氮化物层; 通过在层中等离子体注入原子数等于或小于10的光离子来修饰层，以便形成改性的氮化物层，进行修饰以在其整个厚度上不改变氮化物层 在门的侧面; 以及通过选择性湿法或干法蚀刻，相对于所述半导体材料层和相对于栅极侧面处的非改性层，相对于未改性层，通过选择性湿法或干蚀刻去除修饰的氮化物层，而不蚀刻半导体材料层，其中 在选择性湿法或干蚀刻之后，侧面上未改性层的整个长度保留。

公开(公告)号：US20160276150A1

公开(公告)日：2016-09-22

申请号：US15073444

申请日：2016-03-17

Applicant: APPLIED MATERIALS, INC.

Inventor： Jun Xue ,  Ludovic Godet ,  Srinivas Nemani ,  Michael W. Stowell ,  Qiwei Liang ,  Douglas A. Buchberger

IPC: H01L21/02

CPC classification number: H01L21/02274 ,  H01L21/0217 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831

Abstract: Methods of processing a substrate are provided herein. In some embodiments, a method of processing a substrate disposed in a processing chamber includes: (a) depositing a layer of material on a substrate by exposing the substrate to a first reactive species generated from a remote plasma source and to a first precursor, wherein the first reactive species reacts with the first precursor; and (b) treating all, or substantially all, of the deposited layer of material by exposing the substrate to a plasma generated within the processing chamber from a second plasma source; wherein at least one of the remote plasma source or the second plasma source is pulsed to control periods of depositing and periods of treating.

Abstract translation: 本文提供了处理基板的方法。 在一些实施例中，处理设置在处理室中的衬底的方法包括：（a）通过将衬底暴露于从远程等离子体源产生的第一反应物质和第一前体而在衬底上沉积材料层，其中 第一活性物质与第一前体反应; 和（b）通过将衬底暴露于处理室内从等离子体源产生的等离子体处理所有或基本上全部沉积的材料层; 其中所述远程等离子体源或所述第二等离子体源中的至少一个被脉冲以控制沉积周期和处理周期。

公开(公告)号：US20150170879A1

公开(公告)日：2015-06-18

申请号：US14108683

申请日：2013-12-17

Applicant: Applied Materials, Inc.

Inventor： Andrew Nguyen ,  Kartik Ramaswamy ,  Srinivas Nemani ,  Bradley Howard ,  Yogananda Sarode Vishwanath

IPC: H01J37/32

CPC classification number: H01J37/32091 ,  H01J37/32449 ,  H01J37/32477

Abstract: An exemplary semiconductor processing system may include a high-frequency electrical source that has an outlet plug. The system may include a processing chamber having a top plate, and an inlet assembly coupled with the top plate. The inlet assembly may include an electrode defining an aperture at a first end and configured to receive the outlet plug. The aperture may be characterized at the first end by a first diameter, and a second end of the aperture opposite the first end may be characterized by a second diameter less than the first diameter. The inlet assembly may further include an inlet insulator coupled with the top plate and configured to electrically insulate the top plate from the electrode.

Abstract translation: 示例性的半导体处理系统可以包括具有出口插头的高频电源。 该系统可以包括具有顶板的处理室和与顶板联接的入口组件。 入口组件可以包括在第一端限定孔并且被配置为接收出口塞的电极。 孔可以在第一端被表征为第一直径，并且与第一端相对的孔的第二端的特征在于小于第一直径的第二直径。 入口组件还可包括与顶板耦合的入口绝缘体并且构造成使顶板与电极电绝缘。

公开(公告)号：US12057329B2

公开(公告)日：2024-08-06

申请号：US15828112

申请日：2017-11-30

Applicant: Applied Materials, Inc.

Inventor： Bhargav Citla ,  Chentsau Ying ,  Srinivas Nemani ,  Viachslav Babayan ,  Michael Stowell

IPC: H01L21/00 ,  H01J37/32 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687 ,  H01L21/3105

CPC classification number: H01L21/67069 ,  H01J37/32146 ,  H01J37/32706 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/6831 ,  H01L21/6833 ,  H01L21/68735 ,  H01J2237/334 ,  H01L21/3105

Abstract: Semiconductor systems and methods may include methods of performing selective etches that include modifying a material on a semiconductor substrate. The substrate may have at least two exposed materials on a surface of the semiconductor substrate. The methods may include forming a low-power plasma within a processing chamber housing the semiconductor substrate. The low-power plasma may be a radio-frequency (“RF”) plasma, which may be at least partially formed by an RF bias power operating between about 10 W and about 100 W in embodiments. The RF bias power may also be pulsed at a frequency below about 5,000 Hz. The methods may also include etching one of the at least two exposed materials on the surface of the semiconductor substrate at a higher etch rate than a second of the at least two exposed materials on the surface of the semiconductor substrate.

公开(公告)号：US11410860B2

公开(公告)日：2022-08-09

申请号：US17145194

申请日：2021-01-08

Applicant: Applied Materials, Inc.

Inventor： Dmitry Lubomirsky ,  Srinivas Nemani ,  Ellie Yieh ,  Sergey G. Belostotskiy

IPC: H01L21/67 ,  H01L21/3065 ,  H01J37/32 ,  C23C16/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/683 ,  H01L21/02

Abstract: Methods and process chambers for etching of low-k and other dielectric films are described. For example, a method includes modifying portions of the low-k dielectric layer with a plasma process. The modified portions of the low-k dielectric layer are etched selectively over a mask layer and unmodified portions of the low-k dielectric layer. Etch chambers having multiple chamber regions for alternately generating distinct plasmas are described. In embodiments, a first charge coupled plasma source is provided to generate an ion flux to a workpiece in one operational mode, while a secondary plasma source is provided to provide reactive species flux without significant ion flux to the workpiece in another operational mode. A controller operates to cycle the operational modes repeatedly over time to remove a desired cumulative amount of the dielectric material.

公开(公告)号：US10675581B2

公开(公告)日：2020-06-09

申请号：US16055929

申请日：2018-08-06

Applicant: Applied Materials, Inc.

Inventor： Adib Khan ,  Qiwei Liang ,  Sultan Malik ,  Srinivas Nemani ,  Rafika Smati ,  Joseph Ng ,  John O'Hehir

IPC: H01L21/673 ,  B01D53/047 ,  B01D53/04 ,  H01L21/67

Abstract: Embodiments of the present disclosure relate to gas abatement apparatus and effluent management. The apparatus described herein include a high pressure process chamber and a containment chamber surrounding the process chamber. A high pressure fluid delivery module is in fluid communication with the high pressure process chamber and is configured to deliver a high pressure fluid to the process chamber. An effluent management module includes a muffler assembly to effluent pressure reduction and a plurality of scrubbers provide for treatment of effluent.

公开(公告)号：US10062602B2

公开(公告)日：2018-08-28

申请号：US14142124

申请日：2013-12-27

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  CNRS Centre National de la Recherche Scientifique ,  APPLIED MATERIALS, Inc.

Inventor： Nicolas Posseme ,  Sebastien Barnola ,  Olivier Joubert ,  Srinivas Nemani ,  Laurent Vallier

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76802 ,  H01L21/02063 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76814 ,  H01L2221/1063

Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.