公开(公告)号：US20240301552A1

公开(公告)日：2024-09-12

申请号：US18119432

申请日：2023-03-09

Applicant: APPLIED MATERIALS, INC. ,  The Regents of the University of California

Inventor： Harshil Kashyap ,  Andrew C. Kummel ,  Ajay Kumar Yadav ,  Keith T. Wong ,  Srinivas Nemani ,  Ellie Yieh

IPC: C23C16/455 ,  C23C16/24 ,  C23C16/40

CPC classification number: C23C16/45529 ,  C23C16/24 ,  C23C16/40 ,  C23C16/45546 ,  C23C16/45553

Abstract: Described herein is a method for performing an atomic layer deposition process to form a silicon doped oxide film on a surface of the substrate. The oxide film may be a hafnium-zirconium oxide film, or a zirconium oxide film. The atomic layer deposition process may include forming the oxide layers and a silicon layer using a hydrogen peroxide as at least one of the precursors used in formation of the oxide layers.

公开(公告)号：US20210134618A1

公开(公告)日：2021-05-06

申请号：US17145194

申请日：2021-01-08

Applicant: Applied Materials, Inc.

Inventor： Dmitry Lubomirsky ,  Srinivas Nemani ,  Ellie Yieh ,  Sergey G. Belostotskiy

IPC: H01L21/67 ,  H01L21/3065 ,  H01J37/32 ,  C23C16/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/683

Abstract: Methods and process chambers for etching of low-k and other dielectric films are described. For example, a method includes modifying portions of the low-k dielectric layer with a plasma process. The modified portions of the low-k dielectric layer are etched selectively over a mask layer and unmodified portions of the low-k dielectric layer. Etch chambers having multiple chamber regions for alternately generating distinct plasmas are described. In embodiments, a first charge coupled plasma source is provided to generate an ion flux to a workpiece in one operational mode, while a secondary plasma source is provided to provide reactive species flux without significant ion flux to the workpiece in another operational mode. A controller operates to cycle the operational modes repeatedly over time to remove a desired cumulative amount of the dielectric material.

公开(公告)号：US10790183B2

公开(公告)日：2020-09-29

申请号：US16407510

申请日：2019-05-09

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Keith Tatseun Wong ,  Kurtis Leschkies ,  Namsung Kim ,  Srinivas Nemani

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure is oxidized by a high pressure oxidation process to form a buried oxide layer adjacent the substrate.

公开(公告)号：US20160300709A1

公开(公告)日：2016-10-13

申请号：US15091916

申请日：2016-04-06

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  CNRS Centre National de la Recherche Scientifique ,  APPLIED MATERIALS, Inc.

Inventor： Nicolas POSSEME ,  Thibaut David ,  Olivier Joubert ,  Thorsten Lill ,  Srinivas Nemani ,  Laurent Vallier

IPC: H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306

CPC classification number: H01L21/0234 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L29/66628 ,  H01L29/66772

Abstract: A method is provided for forming spacers for a gate of a field effect transistor, the gate being situated above a layer of semiconductor material, including forming a layer of nitride covering the gate; modifying the layer by plasma implantation of light ions, having an atomic number equal or less than 10, in the layer in order to form a modified layer of nitride, the modifying being performed so as not to modify the layer of nitride over its entire thickness at flanks of the gate; and removing the modified layer of nitride by a selective wet or dry etching, of the modified layer relative to said layer of semiconductor material and relative to the non-modified layer at the flanks of the gate, without etching the layer of semiconductor material, wherein an entire length of the non-modified layer at the flanks remains after the selective wet or dry etching.

Abstract translation: 提供一种用于形成场效应晶体管的栅极的间隔物的方法，栅极位于半导体材料层之上，包括形成覆盖栅极的氮化物层; 通过在层中等离子体注入原子数等于或小于10的光离子来修饰层，以便形成改性的氮化物层，进行修饰以在其整个厚度上不改变氮化物层 在门的侧面; 以及通过选择性湿法或干法蚀刻，相对于所述半导体材料层和相对于栅极侧面处的非改性层，相对于未改性层，通过选择性湿法或干蚀刻去除修饰的氮化物层，而不蚀刻半导体材料层，其中 在选择性湿法或干蚀刻之后，侧面上未改性层的整个长度保留。

公开(公告)号：US20150170943A1

公开(公告)日：2015-06-18

申请号：US14108719

申请日：2013-12-17

Applicant: Applied Materials, Inc.

Inventor： Andrew Nguyen ,  Kartik Ramaswamy ,  Srinivas Nemani ,  Bradley Howard ,  Yogananada Sarode Vishwanath

IPC: H01L21/67 ,  H01L21/3065

CPC classification number: H01L21/3065 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/321 ,  H01J37/32357 ,  H01J37/3244

Abstract: An exemplary semiconductor processing system may include a processing chamber and a first plasma source. The first plasma source may utilize a first electrode positioned externally to the processing chamber, and the first plasma source may be configured to generate a first plasma. The processing system may further comprise a second plasma source separate from the first plasma source that utilizes a second electrode separate from the first electrode. The second electrode may be positioned externally to the processing chamber, and the second plasma source may be configured to generate a second plasma within the processing chamber. The processing system may further comprise a showerhead disposed between the relative locations of the first plasma electrode and the second plasma electrode.

Abstract translation: 示例性的半导体处理系统可以包括处理室和第一等离子体源。 第一等离子体源可以利用位于处理室外部的第一电极，并且第一等离子体源可以被配置为产生第一等离子体。 处理系统还可以包括与第一等离子体源分离的第二等离子体源，其利用与第一电极分开的第二电极。 第二电极可以位于处理室的外部，并且第二等离子体源可以被配置为在处理室内产生第二等离子体。 处理系统还可以包括布置在第一等离子体电极和第二等离子体电极的相对位置之间的喷头。

公开(公告)号：US20150170924A1

公开(公告)日：2015-06-18

申请号：US14108692

申请日：2013-12-17

Applicant: Applied Materials, Inc.

Inventor： Andrew Nguyen ,  Kartik Ramaswamy ,  Srinivas Nemani ,  Bradley Howard ,  Yogananda Sarode Vishwanath

IPC: H01L21/3065 ,  C23C16/513 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/311

CPC classification number: H01J37/32495 ,  H01J37/32091 ,  H01J37/32357 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32532 ,  H01J37/32568 ,  H01J37/32807 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67069

Abstract: An exemplary semiconductor processing system may include a remote plasma source coupled with a processing chamber having a top plate. An inlet assembly may be used to couple the remote plasma source with the top plate and may include a mounting assembly, which in embodiments may include at least two components. The inlet assembly may further include a precursor distribution assembly defining a plurality of distribution channels fluidly coupled with an injection port.

Abstract translation: 示例性半导体处理系统可以包括与具有顶板的处理室耦合的远程等离子体源。 入口组件可以用于将远程等离子体源与顶板耦合，并且可以包括安装组件，其在实施例中可以包括至少两个组件。 入口组件还可以包括限定与注射口流体连接的多个分配通道的前体分布组件。

公开(公告)号：US10964527B2

公开(公告)日：2021-03-30

申请号：US16401883

申请日：2019-05-02

Applicant: Applied Materials, Inc.

Inventor： Jong Mun Kim ,  Biao Liu ,  Cheng Pan ,  Erica Chen ,  Chentsau Ying ,  Srinivas Nemani ,  Ellie Yieh

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/311

Abstract: Methods for removing residuals after a selective deposition process are provided. In one embodiment, the method includes performing a selective deposition process to form a metal containing dielectric material at a first location of a substrate and performing a residual removal process to remove residuals from a second location of the substrate.

公开(公告)号：US10923367B2

公开(公告)日：2021-02-16

申请号：US16107845

申请日：2018-08-21

Applicant: Applied Materials, Inc.

Inventor： Dmitry Lubomirsky ,  Srinivas Nemani ,  Ellie Yieh ,  Sergey G. Belostotskiy

IPC: C23C14/24 ,  H01L21/67 ,  H01L21/3065 ,  H01J37/32 ,  C23C16/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/683 ,  H01L21/02

Abstract: Methods and process chambers for etching of low-k and other dielectric films are described. For example, a method includes modifying portions of the low-k dielectric layer with a plasma process. The modified portions of the low-k dielectric layer are etched selectively over a mask layer and unmodified portions of the low-k dielectric layer. Etch chambers having multiple chamber regions for alternately generating distinct plasmas are described. In embodiments, a first charge coupled plasma source is provided to generate an ion flux to a workpiece in one operational mode, while a secondary plasma source is provided to provide reactive species flux without significant ion flux to the workpiece in another operational mode. A controller operates to cycle the operational modes repeatedly over time to remove a desired cumulative amount of the dielectric material.

公开(公告)号：US20180082861A1

公开(公告)日：2018-03-22

申请号：US15828112

申请日：2017-11-30

Applicant: Applied Materials, Inc.

Inventor： Bhargav Citla ,  Chentsau Ying ,  Srinivas Nemani ,  Viachslav Babayan ,  Michael Stowell

IPC: H01L21/67 ,  H01L21/687 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/683

Abstract: Semiconductor systems and methods may include methods of performing selective etches that include modifying a material on a semiconductor substrate. The substrate may have at least two exposed materials on a surface of the semiconductor substrate. The methods may include forming a low-power plasma within a processing chamber housing the semiconductor substrate. The low-power plasma may be a radio-frequency (“RF”) plasma, which may be at least partially formed by an RF bias power operating between about 10 W and about 100 W in embodiments. The RF bias power may also be pulsed at a frequency below about 5,000 Hz. The methods may also include etching one of the at least two exposed materials on the surface of the semiconductor substrate at a higher etch rate than a second of the at least two exposed materials on the surface of the semiconductor substrate.

公开(公告)号：US20160217981A1

公开(公告)日：2016-07-28

申请号：US15068811

申请日：2016-03-14

Applicant: Applied Materials, Inc.

Inventor： Andrew Nguyen ,  Kartik Ramaswamy ,  Srinivas Nemani ,  Bradley Howard ,  Yogananda Sarode Vishwanath

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/32495 ,  H01J37/32091 ,  H01J37/32357 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32532 ,  H01J37/32568 ,  H01J37/32807 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136 ,  H01L21/67069

Abstract: An exemplary semiconductor processing system may include a remote plasma source coupled with a processing chamber having a top plate. An inlet assembly may be used to couple the remote plasma source with the top plate and may include a mounting assembly, which in embodiments may include at least two components. The inlet assembly may further include a precursor distribution assembly defining a plurality of distribution channels fluidly coupled with an injection port.