公开(公告)号：US20140110248A1

公开(公告)日：2014-04-24

申请号：US14036057

申请日：2013-09-25

Applicant: Applied Materials, Inc.

Inventor： Yong CAO ,  Thanh X. NGUYEN ,  Muhammad M. RASHEED ,  Xianmin TANG

IPC: C23C14/34

CPC classification number: C23C14/34 ,  C23C14/0036 ,  C23C14/35

Abstract: According to embodiments provide a method for forming dielectric films using physical vapor deposition chamber. Particularly, a pasting process may be performed to apply a conductive coating over inner surfaces of the physical vapor deposition chamber. The pasting process may be performed under adjusted process parameters, such as increased spacing and/or increased chamber pressure. The adjusted parameters allow the conductive coating to be formed more efficiently and effectively.

Abstract translation: 根据实施例提供使用物理气相沉积室形成介电膜的方法。 特别地，可以执行粘贴工艺以在物理气相沉积室的内表面上施加导电涂层。 糊化过程可以在调整的工艺参数下进行，例如间隔增加和/或增加的室压力。 经调整的参数可以更有效和更有效地形成导电涂层。

公开(公告)号：US20230187191A1

公开(公告)日：2023-06-15

申请号：US18109130

申请日：2023-02-13

Applicant: Applied Materials, Inc.

Inventor： Kirankumar Neelasandra SAVANDAIAH ,  Shane LAVAN ,  Sundarapandian Ramalinga Vijayalakshmi REDDY ,  Randal Dean SCHMIEDING ,  Yong CAO

IPC: H01J37/34 ,  C23C14/28 ,  C23C14/56 ,  H01J37/32 ,  C23C14/35

CPC classification number: H01J37/3441 ,  C23C14/28 ,  C23C14/35 ,  C23C14/564 ,  H01J37/3411 ,  H01J37/3447 ,  H01J37/3488 ,  H01J37/32504

Abstract: Embodiments of process shield for use in process chambers are provided herein. In some embodiments, a process shield for use in a process chamber includes: an annular body having an upper portion and a lower portion extending downward and radially inward from the upper portion, wherein the upper portion includes a plurality of annular trenches on an upper surface thereof and having a plurality of slots disposed therebetween to fluidly couple the plurality of annular trenches, wherein one or more inlets extend from an outer surface of the annular body to an outermost trench of the plurality of annular trenches.

公开(公告)号：US20210062325A1

公开(公告)日：2021-03-04

申请号：US17003969

申请日：2020-08-26

Applicant: Applied Materials, Inc.

Inventor： Jothilingam RAMALINGAM ,  Xiaozhou CHE ,  Yong CAO ,  Shane LAVAN ,  Chunming ZHOU

IPC: C23C14/35 ,  H01L21/02 ,  H01J37/32 ,  H01J37/34 ,  C23C14/06

Abstract: A method of depositing a backside film layer on a backside of a substrate includes loading a substrate having one or more films deposited on a front side of the substrate onto a substrate support of a processing chamber, depositing, from the sputter target, a target material on the backside of the substrate to form a backside layer on the backside of the substrate, and applying an RF bias to an electrode disposed within the substrate support while depositing the target material. The front side of the substrate faces the substrate support and is spaced from a top surface of the substrate support, and a backside of the substrate faces a sputter target of the processing chamber.

公开(公告)号：US20190189433A1

公开(公告)日：2019-06-20

申请号：US16237407

申请日：2018-12-31

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Mehul B. NAIK ,  Yong CAO ,  Yana CHENG ,  Weifeng YE

IPC: H01L21/02 ,  H01L21/768

CPC classification number: H01L21/02167 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/76826 ,  H01L21/76832

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

公开(公告)号：US20170125215A1

公开(公告)日：2017-05-04

申请号：US14986168

申请日：2015-12-31

Applicant: APPLIED MATERIALS, INC.

Inventor： Yana CHENG ,  Zhefeng LI ,  Chi Hong CHING ,  Yong CAO ,  Rongjun WANG

IPC: H01J37/32 ,  C23C14/34

Abstract: Methods are disclosed for depositing a thin film of compound material on a substrate. In some embodiments, a method of depositing a layer of compound material on a substrate include: flowing a reactive gas into a plasma processing chamber having a substrate to be sputter deposited disposed therein in opposition to a sputter target comprising a metal; exciting the reactive gas into a reactive gas plasma to react with the sputter target and to form a first layer of compound material thereon; flowing an inert gas into the plasma processing chamber; and exciting the inert gas into a plasma to sputter a second layer of the compound material onto the substrate directly from the first layer of compound material. The cycles of target poisoning and sputtering may be repeated until a compound material layer of appropriate thickness has been formed on the substrate.

公开(公告)号：US20150114827A1

公开(公告)日：2015-04-30

申请号：US14062610

申请日：2013-10-24

Applicant: Applied Materials, Inc.

Inventor： Yong CAO ,  Tingjun XU ,  Rajkumar JAKKARAJU ,  Rongjun WANG

IPC: H01L21/02 ,  C23C14/34

CPC classification number: H01L21/02266 ,  C23C14/0036 ,  C23C14/0676 ,  H01L21/02178 ,  H01L21/31111

Abstract: Methods for forming a metal dielectric etching stop layer onto a substrate with good etching selectivity and low wet etching rate. In one embodiment, a method of sputter depositing a metal dielectric etching stop layer on the substrate includes transferring a substrate in a processing chamber, supplying a gas mixture including at least N2 gas into the processing chamber, applying a RF power to form a plasma from the gas mixture to sputter source material from a target disposed in the processing chamber, maintaining a substrate temperature less than about 320 degrees Celsius, and depositing a metal dielectric etching stop layer onto the substrate from the sputtered source material.

Abstract translation: 在具有良好蚀刻选择性和低湿蚀刻速率的基板上形成金属电介质蚀刻停止层的方法。 在一个实施例中，在衬底上溅射沉积金属电介质蚀刻停止层的方法包括在处理室中转移衬底，将至少包括N 2气体的气体混合物供应到处理室中，施加RF功率以形成等离子体 所述气体混合物从设置在所述处理室中的靶溅射源材料，保持低于约320摄氏度的衬底温度，以及从所述溅射源材料在所述衬底上沉积金属电介质蚀刻停止层。

公开(公告)号：US20140327117A1

公开(公告)日：2014-11-06

申请号：US14269010

申请日：2014-05-02

Applicant: Applied Materials, Inc.

Inventor： Christopher Dennis BENCHER ,  Daniel Lee DIEHL ,  Huixiong DAI ,  Yong CAO ,  Tingjun XU ,  Weimin (Wilson) ZENG ,  Peng XIE

IPC: H01L21/033

CPC classification number: H01L21/0337 ,  C23C14/0042 ,  C23C14/06 ,  C23C14/14 ,  C23C14/351 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02266 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31138 ,  H01L21/31144

Abstract: The embodiments herein provides methods for forming a PVD silicon oxide or silicon rich oxide, or PVD SiN or silicon rich SiN, or SiC or silicon rich SiC, or combination of the preceding including a variation which includes controlled doping of hydrogen into the compounds heretofore referred to as SiOxNyCz:Hw, where w, x, y, and z can vary in concentration from 0% to 100%, is produced as a hardmask with optical properties that are substantially matched to the photo-resists at the exposure wavelength. Thus making the hardmask optically planarized with respect to the photo-resist. This allows for multiple sequences of litho and etches in the hardmask while the photo-resist maintains essentially no optical topography or reflectivity variations.

Abstract translation: 本文的实施方案提供了用于形成PVD氧化硅或富硅氧化物或PVD SiN或富硅SiN或富SiC或富硅SiC的方法或前述组合，包括将氢控制掺入到迄今为止参考的化合物 作为SiO x N y C z：H w，其中w，x，y和z可以在0％至100％的浓度范围内变化，作为具有与曝光波长下的光致抗蚀剂基本匹配的光学性质的硬掩模。 因此使相对于光致抗蚀剂光学平坦化的硬掩模。 这允许在硬掩模中的多个序列的光刻和蚀刻，而光致抗蚀剂基本上保持没有光学形貌或反射率变化。

公开(公告)号：US20140042016A1

公开(公告)日：2014-02-13

申请号：US14054477

申请日：2013-10-15

Applicant: Applied Materials, Inc.

Inventor： Yong CAO ,  Xianmin TANG ,  Srinivas GANDIKOTA ,  Wei D. WANG ,  Zhendong LIU ,  Kevin MORAES ,  Muhammad M. RASHEED ,  Thanh X. NGUYEN ,  Ananthkrishna JUPUDI

IPC: H01L21/28 ,  H01L21/285

CPC classification number: H01L21/28079 ,  C23C14/165 ,  C23C14/345 ,  C23C14/35 ,  H01L21/28088 ,  H01L21/2855 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

Abstract: Embodiments described herein provide a semiconductor device and methods and apparatuses of forming the same. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal nitride film layer on the conductive film layer, depositing a silicon-containing film layer on the refractory metal nitride film layer, and depositing a tungsten film layer on the silicon-containing film layer.

Abstract translation: 本文所述的实施例提供了一种半导体器件及其形成方法和装置。 半导体器件包括在源极和漏极区域之间的衬底上具有源极和漏极区域以及栅电极堆叠的衬底。 在一个实施例中，该方法包括将衬底定位在处理室内，其中衬底包括源极和漏极区域，源极和漏极区域之间的栅极介电层以及栅极电介质层上的导电膜层。 该方法还包括在导电膜层上沉积难熔金属氮化物膜层，在难熔金属氮化物膜层上沉积含硅膜层，并在含硅膜层上沉积钨膜层。