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    Method of using vertically configured chamber used for multiple processes
    21.
    发明授权
    Method of using vertically configured chamber used for multiple processes 有权
    使用垂直配置的室用于多个过程的方法

    公开(公告)号：US06969456B2

    公开(公告)日：2005-11-29

    申请号：US10041029

    申请日：2001-12-28

    Applicant: Konstantin Volodarsky ,  Boguslaw A. Nagorski ,  Rimma Volodarsky ,  Douglas W. Young ,  Cyprian Uzoh ,  Homayoun Talieh

    Inventor： Konstantin Volodarsky ,  Boguslaw A. Nagorski ,  Rimma Volodarsky ,  Douglas W. Young ,  Cyprian Uzoh ,  Homayoun Talieh

    IPC: C25D7/12 ,  H01L21/00 ,  H01L21/02 ,  H01L21/3063 ,  C25F3/00 ,  B08B3/04

    CPC classification number: H01L21/6719 ,  C25D7/12 ,  C25D17/001 ,  H01L21/67028 ,  Y10S134/902

    Abstract: The present invention relates to a containment chamber that is used for carrying out multiple processing steps such as depositing on, polishing, etching, modifying, rinsing, cleaning, and drying a surface on the workpiece. In one example of the present invention, the chamber is used to electro chemically mechanically deposit a conductive material on a semiconductor wafer. The same containment chamber can then be used to rinse and clean the same wafer. As a result, the present invention eliminates the need for separate processing stations for depositing the conductive material and cleaning the wafer. Thus, with the present invention, costs and physical space are reduced while providing an efficient apparatus and method for carrying out multiple processes on the wafer surface using a containment chamber.

    Abstract translation: 本发明涉及一种用于进行多个处理步骤的容纳室，例如沉积，抛光，蚀刻，改性，漂洗，清洁和干燥工件上的表面。 在本发明的一个实例中，室用于在半导体晶片上化学机械地沉积导电材料。 然后可以使用相同的容纳室来冲洗和清洁相同的晶片。 结果，本发明消除了对用于沉积导电材料和清洁晶片的单独处理站的需要。 因此，利用本发明，降低了成本和物理空间，同时提供了使用容纳室在晶片表面上执行多个工艺的有效的装置和方法。

    Method and system for optically enhanced metal planarization
    22.
    发明申请
    Method and system for optically enhanced metal planarization 有权
    用于光学增强金属平面化的方法和系统

    公开(公告)号：US20050029123A1

    公开(公告)日：2005-02-10

    申请号：US10637731

    申请日：2003-08-08

    Applicant: Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Halit Yakupoglu

    Inventor： Cyprian Uzoh ,  Homayoun Talieh ,  Bulent Basol ,  Halit Yakupoglu

    IPC: H01L21/321 ,  B29C71/02 ,  B05D5/12

    CPC classification number: H01L21/32125

    Abstract: The methods and systems described provide for radiation assisted material deposition, removal, and planarization at a surface, edge, and/or bevel of a workpiece such as a semiconductor wafer. Exemplary processes performed on a workpiece surface having topographical features include radiation assisted electrochemical material deposition, which produces an adsorbate layer outside of the features to suppress deposition outside of the features and to encourage, through charge conservation, deposition into the features to achieve, for example, a planar surface profile. A further exemplary process is radiation assisted electrochemical removal of material, which produces an adsorbate layer in the features to suppress removal of material from the features and to encourage, through charge conservation, removal of material outside of the features so that, for example, a planar surface profile is achieved.

    Abstract translation: 所描述的方法和系统提供了诸如半导体晶片的工件的表面，边缘和/或斜面处的辐射辅助材料沉积，去除和平坦化。 在具有形貌特征的工件表面上执行的示例性工艺包括辐射辅助电化学材料沉积，其在特征之外产生吸附物层以抑制特征外的沉积，并且通过电荷保存沉积到特征中以实现例如 ，平面表面轮廓。 进一步的示例性方法是材料的辐射辅助电化学去除，其在特征中产生吸附物层以抑制材料从特征中的去除并且通过电荷保持除去特征外的材料，从而例如， 实现了平面表面轮廓。

    Anode assembly for plating and planarizing a conductive layer
    23.
    发明授权
    Anode assembly for plating and planarizing a conductive layer 有权
    用于电镀和平坦化导电层的阳极组件

    公开(公告)号：US06773576B2

    公开(公告)日：2004-08-10

    申请号：US10251377

    申请日：2002-09-20

    Applicant: Rimma Volodarsky ,  Konstantin Volodarsky ,  Cyprian Uzoh ,  Homayoun Talieh ,  Douglas W. Young

    Inventor： Rimma Volodarsky ,  Konstantin Volodarsky ,  Cyprian Uzoh ,  Homayoun Talieh ,  Douglas W. Young

    IPC: C25F302

    CPC classification number: C25D17/14 ,  C25F7/00

    Abstract: A particular anode assembly can be used to supply a solution for any of a plating operation, a planarization operation, and a plating and planarization operation to be performed on a semiconductor wafer. The anode assembly includes a rotatable shaft disposed within a chamber in which the operation is performed, an anode housing connected to the shaft, and a porous pad support plate attached to the anode housing. The support plate has a top surface adapted to support a pad which is to face the wafer, and, together with the anode housing, defines an anode cavity. A consumable anode may be provided in the anode cavity to provide plating material to the solution. A solution delivery structure by which the solution can be delivered to said anode cavity is also provided. The solution delivery structure may be contained within the chamber in which the operation is performed. A shield can also be mounted between the shaft and an associated spindle to prevent leakage of the solution from the chamber.

    Abstract translation: 可以使用特定的阳极组件来提供用于在半导体晶片上进行的电镀操作，平面化操作和电镀和平面化操作中的任何一种的解决方案。 阳极组件包括设置在其中执行操作的室内的可旋转轴，连接到轴的阳极壳体和附接到阳极壳体的多孔垫支撑板。 支撑板具有适于支撑面向晶片的焊盘的顶表面，并且与阳极壳体一起限定阳极腔。 可以在阳极腔中设置消耗性阳极以向溶液提供电镀材料。 还提供了可以将溶液输送到所述阳极腔的溶液输送结构。 溶液输送结构可以包含在进行操作的室内。 护罩还可以安装在轴和相关主轴之间，以防止溶液从腔室泄漏。

    Methods for repairing defects on a semiconductor substrate
    24.
    发明授权
    Methods for repairing defects on a semiconductor substrate 有权
    用于修复半导体衬底上的缺陷的方法

    公开(公告)号：US06582579B1

    公开(公告)日：2003-06-24

    申请号：US09534704

    申请日：2000-03-24

    Applicant: Cyprian Uzoh

    Inventor： Cyprian Uzoh

    IPC: C25D502

    CPC classification number: H01L21/76877 ,  H01L21/2885 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76892

    Abstract: The present invention relates to methods for repairing defects on a semiconductor substrate. This is accomplished by selectively depositing the conductive material in defective portions in the cavities while removing residual portions from the field regions of the substrate. Another method according to the present invention includes forming a uniform conductive material overburden on a top surface of the substrate. The present invention also discloses a method for depositing a second conductive material on the first conductive material of the substrate.

    Abstract translation: 本发明涉及修复半导体衬底上的缺陷的方法。 这是通过在空腔中的缺陷部分中选择性地沉积导电材料而实现的，同时从衬底的场区域去除残余部分。 根据本发明的另一种方法包括在衬底的顶表面上形成均匀的导电材料覆盖层。 本发明还公开了一种在衬底的第一导电材料上沉积第二导电材料的方法。

    LOW STRESS VIAS
    28.
    发明申请
    LOW STRESS VIAS 有权
    低应力VIAS

    公开(公告)号：US20130026645A1

    公开(公告)日：2013-01-31

    申请号：US13193814

    申请日：2011-07-29

    Applicant: Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    Inventor： Ilyas Mohammed ,  Belgacem Haba ,  Cyprian Uzoh

    IPC: H01L23/48 ,  H01L21/283

    CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L2224/10135 ,  H01L2924/07811 ,  H01L2924/00

    Abstract: A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.

    Abstract translation: 部件可以包括具有远离其前表面和后表面的基板，从后表面朝向前表面延伸的开口以及在开口内延伸的导电通孔。 基底可以具有小于10ppm /℃的CTE。开口可以限定前表面和后表面之间的内表面。 导电通孔可以包括覆盖在内表面上的第一金属层和覆盖第一金属层并电耦合到第一金属层的第二金属区域。 第二金属区域可具有大于第一金属层的CTE的CTE。 导电通孔可以在导电通孔的直径上具有小于第二金属区域的CTE的80％的有效CTE。

    SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS
    29.
    发明申请
    SINGLE EXPOSURE IN MULTI-DAMASCENE PROCESS 有权
    多元化过程中的单次接触

    公开(公告)号：US20120326313A1

    公开(公告)日：2012-12-27

    申请号：US13170095

    申请日：2011-06-27

    Applicant: Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

    Inventor： Cyprian Uzoh ,  Vage Oganesian ,  Ilyas Mohammed ,  Craig Mitchell ,  Belgacem Haba

    IPC: H01L23/52 ,  H01L21/768

    CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of fabricating a multi-layer semiconductor device such as a multi-layer damascene or inverted multi-layer damascene structure using only a single or reduced number of exposure steps. The method may include etching a precursor structure formed of materials with differential removal rates for a given removal condition. The method may include removing material from a multi-layer structure under different removal conditions. Further disclosed are multi-layer damascene structures having multiple cavities of different sizes. The cavities may have smooth inner wall surfaces. The layers of the structure may be in direct contact. The cavities may be filled with a conducting metal or an insulator. Multi-layer semiconductor devices using the methods and structures are further disclosed.

    Abstract translation: 仅使用单个或减少数量的曝光步骤来制造多层半导体器件的方法，例如多层镶嵌或倒置的多层镶嵌结构。 该方法可以包括用于对于给定的去除条件蚀刻由具有差异去除速率的材料形成的前体结构。 该方法可以包括在不同的去除条件下从多层结构去除材料。 还公开了具有不同尺寸的多个空腔的多层镶嵌结构。 空腔可以具有平滑的内壁表面。 结构的层可以直接接触。 空腔可以用导电金属或绝缘体填充。 进一步公开了使用这些方法和结构的多层半导体器件。

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