公开(公告)号：US11069606B2

公开(公告)日：2021-07-20

申请号：US16591378

申请日：2019-10-02

Applicant: Compass Technology Company Limited

Inventor： Kelvin Po Leung Pun ,  Chee Wah Cheung

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/16 ,  H01L21/48 ,  H01L23/538 ,  H01L25/00

Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

公开(公告)号：US20190244882A1

公开(公告)日：2019-08-08

申请号：US15887346

申请日：2018-02-02

Applicant: Compass Technology Company Limited

Inventor： Kelvin Po Leung Pun ,  Chee Wah Cheung

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  C23C18/16 ,  C25D3/38 ,  C25D5/02

Abstract: A method to produce a substrate suitable for diffusion bonding is described. A flexible dielectric substrate is provided. An alkaline modification is applied to the dielectric substrate to form a polyamic acid (PAA) anchoring layer on a surface of the dielectric substrate. A Ni—P seed layer is electrolessly plated on the PAA layer. Copper traces are plated within a photoresist pattern on the Ni—P seed layer. A surface finishing layer is electrolytically plated on the copper traces. The photoresist pattern and Ni—P seed layer not covered by the copper traces are removed to complete the substrate suitable for diffusion bonding.

公开(公告)号：US09637376B2

公开(公告)日：2017-05-02

申请号：US15133309

申请日：2016-04-20

Applicant: Compass Technology Company Limited

Inventor： Kelvin Po Leung Pun ,  Chee Wah Cheung

IPC: H01L23/02 ,  B81B7/00 ,  G01C19/00 ,  G01C19/5783 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2201/0242 ,  B81B2207/097 ,  B81C1/00301 ,  G01C19/00 ,  G01C19/5783 ,  H01L2224/48145 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00012

Abstract: An integrated circuit packaging structure comprises at least one Micro Electrical Mechanical Systems (MEMS) gyroscope die mounted directly on a multi-layer flexible substrate having at least one metal layer and wire-bonded to the flexible substrate and a lid or die coating protecting the MEMS die and wire bonds.

公开(公告)号：US11594509B2

公开(公告)日：2023-02-28

申请号：US17164217

申请日：2021-02-01

Applicant: Compass Technology Company Limited

Inventor： Kelvin Po Leung Pun ,  Chee Wah Cheung

IPC: H01L23/00 ,  H01L23/498

Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

公开(公告)号：US11076491B2

公开(公告)日：2021-07-27

申请号：US16654503

申请日：2019-10-16

Applicant: Compass Technology Company Limited

Inventor： Kelvin Po Leung Pun ,  Chee Wah Cheung ,  Jason Rotanson

IPC: H05K1/00 ,  H05K3/36 ,  H05K1/02 ,  H05K1/14

Abstract: An integrated electro-optical circuit board comprises a first flexible substrate having a top side and a bottom side, at least one first optical circuit on the bottom side of the first flexible substrate connected to the top surface through a filled via, at least one first metal trace on the top side of the first flexible substrate, an optical adhesive layer connecting the bottom side of the first flexible substrate to a top side of a second flexible substrate, and at least one second metal trace on a bottom side of the second flexible substrate connected by a filled via through the second flexible substrate, the optical adhesive layer, and the first flexible substrate to the at least one first metal trace.

公开(公告)号：US20210120680A1

公开(公告)日：2021-04-22

申请号：US16654503

申请日：2019-10-16

Applicant: Compass Technology Company Limited

Inventor： Kelvin Po Leung Pun ,  Chee Wah Cheung ,  Jason Rotanson

IPC: H05K3/36 ,  H05K1/02 ,  H05K1/14

Abstract: An integrated electro-optical circuit board comprises a first flexible substrate having a top side and a bottom side, at least one first optical circuit on the bottom side of the first flexible substrate connected to the top surface through a filled via, at least one first metal trace on the top side of the first flexible substrate, an optical adhesive layer connecting the bottom side of the first flexible substrate to a top side of a second flexible substrate, and at least one second metal trace on a bottom side of the second flexible substrate connected by a filled via through the second flexible substrate, the optical adhesive layer, and the first flexible substrate to the at least one first metal trace.

公开(公告)号：US10362680B2

公开(公告)日：2019-07-23

申请号：US15978268

申请日：2018-05-14

Applicant: Compass Technology Company Limited

Inventor： Kelvin Po Leung Pun ,  Chee Wah Cheung

IPC: H05K3/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H01L29/16 ,  G06F3/041 ,  H05K3/02 ,  G06K9/00 ,  H05K1/14 ,  H05K3/38

Abstract: A process for forming a graphene circuit pattern on an object is described. A graphene layer is grown on a metal foil. A bonding layer is formed on a protective film and a surface of the bonding layer is roughened. The graphene layer is transferred onto the roughened surface of the bonding layer. The protective film is removed and the bonding layer is laminated to a first core dielectric substrate. The metal foil is etched away. Thereafter the graphene layer is etched using oxygen plasma etching to form graphene circuits on the first core dielectric substrate. The first core dielectric substrate having graphene circuits thereon is bonded together with a second core dielectric substrate wherein the graphene circuits are on a side facing the second core dielectric substrate wherein an air gap is left there between.

公开(公告)号：US20190043821A1

公开(公告)日：2019-02-07

申请号：US16157494

申请日：2018-10-11

Applicant: Compass Technology Company Limited

Inventor： Kelvin Po Leung Pun ,  Chee Wah Cheung

IPC: H01L23/00

Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

公开(公告)号：US10103095B2

公开(公告)日：2018-10-16

申请号：US15286849

申请日：2016-10-06

Applicant: Compass Technology Company Limited

Inventor： Kelvin Po Leung Pun ,  Chee Wah Cheung

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

公开(公告)号：US09974188B2

公开(公告)日：2018-05-15

申请号：US15090703

申请日：2016-04-05

Applicant: Compass Technology Company Limited

Inventor： Kelvin Po Leung Pun ,  Chee Wah Cheung

IPC: H05K1/09 ,  H05K3/00 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K3/0041 ,  G06F3/041 ,  H05K1/0278 ,  H05K1/0306 ,  H05K1/0326 ,  H05K1/0346 ,  H05K1/09 ,  H05K1/144 ,  H05K3/0064 ,  H05K3/025 ,  H05K3/027 ,  H05K3/381 ,  H05K2201/0141 ,  H05K2201/0145 ,  H05K2201/0154 ,  H05K2201/0323 ,  H05K2201/042 ,  H05K2203/0152 ,  H05K2203/0376 ,  H05K2203/095 ,  H05K2203/1545

Abstract: A process for forming a graphene circuit pattern on an object is described. A graphene layer is grown on a metal foil. A bonding layer is formed on a protective film and a surface of the bonding layer is roughened. The graphene layer is transferred onto the roughened surface of the bonding layer. The protective film is removed and the bonding layer is laminated to a first core dielectric substrate. The metal foil is etched away. Thereafter the graphene layer is etched using oxygen plasma etching to form graphene circuits on the first core dielectric substrate. The first core dielectric substrate having graphene circuits thereon is bonded together with a second core dielectric substrate wherein the graphene circuits are on a side facing the second core dielectric substrate wherein an air gap is left therebetween.