公开(公告)号：US20180278234A1

公开(公告)日：2018-09-27

申请号：US15468710

申请日：2017-03-24

Applicant: Dror Hurwitz

Inventor： Dror Hurwitz

IPC: H03H9/58 ,  H03H9/205 ,  H01L23/00

CPC classification number: H03H9/205 ,  H01L24/13 ,  H01L24/29 ,  H01L2224/0401 ,  H01L2224/13684 ,  H01L2224/29624 ,  H01L2224/29644

Abstract: A filter package comprising an array of piezoelectric films sandwiched between an array of upper electrodes and lower electrodes: the individual piezoelectric films and the upper electrodes being separated by a passivation material; the lower electrode being coupled to an interposer with a first cavity between the lower electrodes and the interposer; the filter package further comprising a silicon wafer of known thickness attached over the upper electrodes with an array of upper cavities between the silicon wafer and a silicon cover; each upper cavity aligned with a piezoelectric film in the array of piezoelectric films, the upper cavities having side walls comprising the passivation material.

公开(公告)号：US20180278227A1

公开(公告)日：2018-09-27

申请号：US15468766

申请日：2017-03-24

Applicant: Dror Hurwitz

Inventor： Dror Hurwitz

IPC: H03H3/02 ,  H01L41/29 ,  H01L41/332 ,  H01L41/08 ,  H01L41/107 ,  H03H9/205 ,  H03H9/54 ,  H01L41/047

CPC classification number: H03H3/02 ,  H03H9/1014 ,  H03H9/581 ,  H03H9/582

Abstract: A method of fabricating an RF filter comprising an array of resonators, the method comprising the steps of: (a) Obtaining a removable carrier with release layer; (b) Growing a piezoelectric film on a removable carrier; (c) Applying a first electrode to the piezoelectric film; (d) Obtaining a backing membrane on a cover, with or without prefabricated cavities between the backing film and cover; (e) Attaching the backing membrane to the first electrode; (f) Detaching the removable carrier; (g) Measuring and trimming the piezoelectric film as necessary; (h) Selectively etching away the piezoelectric layer to fabricate discrete resonator islands; (i) Etching down through coatings backing membrane, silicon dioxide and into silicon handle to form trenches; (j) Applying passivation layer into the trenches and around the piezoelectric islands; (k) Depositing a second electrode layer over the dielectric and piezoelectric film islands; (l) Applying connections for subsequent electrical coupling to an interposer; (m) Selectively remove second electrode material leaving coupled resonator arrays; (n) Create gasket around perimeter of the resonator array; (o) Thinning down cover of handle to desired thickness; (p) Optionally fabricating cavities between the silicon membrane and handle; (q) Dicing the wafer into flip chip single unit filter arrays; (r) Obtaining an interposer; (s) Optionally applying a dam to the interposer surface to halt overfill flow; (t) Coupling the flip chip single unit filter array to pads of the interposer by reflow of the solder cap; (u) Encapsulating with polymer overfill; and (v) Singulating into separate filter modules.

公开(公告)号：US09615447B2

公开(公告)日：2017-04-04

申请号：US13555437

申请日：2012-07-23

Applicant: Dror Hurwitz ,  Alex Huang

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H05K1/02 ,  H01L23/498 ,  H01L23/00 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/11 ,  H05K2201/09781 ,  H01L2924/00

Abstract: A multilayer electronic support structure including at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one constructional element through the dielectric material spanning between said pair of adjacent feature layers in a Z direction perpendicular to the X-Y plane; wherein said at least one constructional element is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane and wherein the at least one constructional element is fully encapsulated within the dielectric material and is electrically isolated from its surrounding.

公开(公告)号：US09440135B2

公开(公告)日：2016-09-13

申请号：US13482045

申请日：2012-05-29

Applicant: Dror Hurwitz

Inventor： Dror Hurwitz

IPC: H05K1/11 ,  A63B69/36 ,  A63B69/00

CPC classification number: A63B69/3685 ,  A63B69/0059 ,  A63B69/36 ,  A63B69/3608 ,  A63B69/3676 ,  A63B2208/0204 ,  H01L21/4846 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilayer electronic support structure comprising at least one pair of adjacent feature layers extending in an X-Y plane that are separated by a via layer; said via layer comprising a dielectric material that is sandwiched between the two adjacent feature layers and at least one one non-cylindrical via post that couples said pair of adjacent feature layers through the dielectric material in a Z direction perpendicular to the X-Y plane; wherein said at least one non-cylindrical via post is characterized by having a long dimension in the X-Y plane that is at least 3 times as long as a short dimension in the X-Y plane.

Abstract translation: 一种多层电子支撑结构，包括在X-Y平面中延伸的至少一对相邻特征层，所述相邻特征层由通孔层分隔开; 所述通孔层包括夹在两个相邻特征层之间的介电材料和至少一个非圆柱形通孔，其在垂直于X-Y平面的Z方向上将所述一对相邻特征层通过电介质材料连接; 其中所述至少一个非圆柱形通孔的特征在于在X-Y平面中具有至少3倍于X-Y平面中的短尺寸的长尺寸。

公开(公告)号：US09161461B2

公开(公告)日：2015-10-13

申请号：US13523116

申请日：2012-06-14

Applicant: Dror Hurwitz ,  Simon Chan ,  Alex Huang

Inventor： Dror Hurwitz ,  Simon Chan ,  Alex Huang

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/46 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K3/4697 ,  H01L21/4857 ,  H01L23/3677 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/308 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A multilayer electronic structure comprising a plurality of layers extending in an X-Y plane consisting of a dielectric material surrounding metal via posts that conduct in a Z direction perpendicular to the X-Y plane, wherein at least one multilayered hole crosses at least two layers of the plurality of layers and comprises at least two hole layers in adjacent layers of the multilayer composite electronic structure, wherein the at least two holes in adjacent layers have different dimensions in the X-Y plane, such that a perimeter of the multilayered hole is stepped and where at least one hole is an aperture to a surface of the multilayer electronic structure.

Abstract translation: 一种多层电子结构，包括在XY平面中延伸的多个层，所述多个层由围绕金属通孔的介电材料构成，所述介电材料围绕垂直于所述XY平面的Z方向传导，其中至少一个多层孔穿过所述多个 层，并且在多层复合电子结构的相邻层中包括至少两个孔层，其中相邻层中的至少两个孔在XY平面中具有不同的尺寸，使得多层孔的周边是阶梯状的，并且其中至少一个 孔是多层电子结构的表面的孔。

公开(公告)号：US09137905B2

公开(公告)日：2015-09-15

申请号：US13531948

申请日：2012-06-25

Applicant: Dror Hurwitz ,  Simon Chan

Inventor： Dror Hurwitz ,  Simon Chan

IPC: H01L21/00 ,  H05K3/46 ,  H01L21/48 ,  H01L23/498

CPC classification number: H05K3/4679 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K3/4647 ,  H05K2203/025 ,  H01L2924/00

Abstract: A process for alignment a subsequent layer over a previous layer comprising metal features or vias encapsulated in dielectric material comprising the steps of: thinning and planarizing the dielectric material to create a smooth surface of dielectric material and coplanar exposed ends of the via posts; imaging the smooth surface; discerning the position of the end of at least one feature, and using the position of the end of at least one via feature as a registration mark for aligning the subsequent layer.

Abstract translation: 一种用于使包含在介电材料中的金属特征或通孔的先前层之后的对准对齐的方法，包括以下步骤：使介电材料变薄和平坦化，以形成介电材料的平滑表面和通孔的共面暴露端; 成像光滑表面; 识别至少一个特征的末端的位置，以及使用至少一个通孔特征的末端的位置作为对准随后层的对准标记。

公开(公告)号：US08987602B2

公开(公告)日：2015-03-24

申请号：US13523102

申请日：2012-06-14

Applicant: Dror Hurwitz ,  Alex Huang

Inventor： Dror Hurwitz ,  Alex Huang

IPC: H05K1/11 ,  H05K1/09 ,  H05K3/46 ,  H05K1/02

CPC classification number: H01L23/3677 ,  H01L21/486 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16238 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1531 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A laminated multilayer electronic support structure comprising a dielectric with integral vias and feature layers and further comprising a planar metal core characterized by a thickness of less than 100 microns.

Abstract translation: 一种层叠多层电子支撑结构，其包括具有整体通孔和特征层的电介质，并且还包括平面金属芯，其特征在于小于100微米的厚度。

公开(公告)号：US06280640B1

公开(公告)日：2001-08-28

申请号：US09303422

申请日：1999-05-03

Applicant: Dror Hurwitz ,  Boris Yofis ,  Dror Katz ,  Eva Igner

Inventor： Dror Hurwitz ,  Boris Yofis ,  Dror Katz ,  Eva Igner

IPC: H01B1300

CPC classification number: H05K3/4647 ,  H01L21/4846 ,  H01L21/4857 ,  H01L23/498 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K2203/0315 ,  H05K2203/1142 ,  H01L2924/00

Abstract: A process for manufacturing a chip carrier substrate, the process including the steps of providing a first layer of copper conductor on a substrate, forming a first layer of barrier metal on the first layer of copper conductor, forming a layer of aluminum on the first layer of barrier metal, forming a second barrier metal on the aluminum layer, patterning the top barrier metal in the form of studs, anodizing the aluminum unprotected by the top barrier metal, removing the aluminum oxide and patterning the first copper layer, removing all the exposed barrier metal; surrounding the studs and the copper conductor with a polymeric dielectric; polishing the polymeric dielectric to expose the studs; and forming a second layer of copper conductor on the planar polymeric dielectric.

Abstract translation: 一种制造芯片载体衬底的方法，该方法包括以下步骤：在衬底上提供第一铜导体层，在第一层铜导体上形成第一层阻挡金属层，在第一层上形成一层铝层 的阻挡金属，在铝层上形成第二阻挡金属，将顶部阻挡金属图案化成螺柱形式，阳极氧化未被顶部阻挡金属保护的铝，去除氧化铝并图案化第一铜层，去除所有暴露的 阻隔金属; 用聚合物电介质围绕螺栓和铜导体; 抛光聚合物电介质以暴露螺柱; 以及在所述平面聚合物电介质上形成第二层铜导体。

公开(公告)号：US06262478B1

公开(公告)日：2001-07-17

申请号：US09310328

申请日：1999-05-12

Applicant: Dror Hurwitz ,  Eva Igner ,  Boris Yofis ,  Dror Katz

Inventor： Dror Hurwitz ,  Eva Igner ,  Boris Yofis ,  Dror Katz

IPC: H01L23053

CPC classification number: H01L21/76885 ,  H01L23/53223 ,  H01L23/5329 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A process for manufacturing an electronic interconnect structure, the process including the steps of depositing an adhesion metal layer over a dielectric material surface having at least one exposed aluminum surface; depositing a barrier metal layer over the adhesion metal layer; depositing a first layer of aluminum over the barrier metal layer; depositing an intermediate barrier metal layer over the first layer of aluminum; applying a photoresist layer on top of the intermediate barrier metal layer; exposing and developing the photoresist layer; removing the exposed barrier metal and photoresist layer, leaving a layer of barrier metal over the aluminum layer; converting those portions of the layer of aluminum which are not covered by barrier metal to a porous aluminum oxide by porous anodization; removing the porous aluminum oxide; and removing the exposed barrier metal and adhesion metal layers to leave exposed patterned aluminum, and an electronic interconnect structure manufactured by this method.

Abstract translation: 一种用于制造电子互连结构的方法，该方法包括以下步骤：在具有至少一个暴露的铝表面的电介质材料表面上沉积粘附金属层; 在所述粘附金属层上沉积阻挡金属层; 在阻挡金属层上沉积第一层铝; 在第一层铝上沉积中间阻挡金属层; 在中间阻挡金属层的顶部上施加光致抗蚀剂层; 曝光和显影光致抗蚀剂层; 去除暴露的阻挡金属和光致抗蚀剂层，在铝层上留下一层阻挡金属; 通过多孔阳极氧化将未被阻挡金属覆盖的铝层的那些部分转化成多孔氧化铝; 去除多孔氧化铝; 并且去除暴露的阻挡金属和粘合金属层以留下暴露的图案化铝，以及通过该方法制造的电子互连结构。