公开(公告)号：US4814756A

公开(公告)日：1989-03-21

申请号：US9578

申请日：1987-01-28

Applicant: Gerard Chauvel

Inventor： Gerard Chauvel

IPC: G06F5/10 ,  G06F5/12 ,  G06F5/14 ,  G09G5/34 ,  G09G5/40 ,  H04N7/025 ,  H04N7/035 ,  G09G1/16

CPC classification number: G06F5/14 ,  G06F5/12 ,  G09G5/343 ,  G09G5/40 ,  H04N7/0255 ,  H04N7/035 ,  G06F2205/123

Abstract: A system for displaying alphanumeric and graphic information on a raster scanned display device, for example, in a teletext system, includes a memory which is updated to change the display. Dynamic changes in the displayed image are provided by assigning a base address to each of one or more zones in the memory and altering the base addresses as required under local or remote control. Alphanumeric and graphic data may be combined on a single displayed page by means of identification data associated with each row or line of data to be displayed. The required capacity of the memory associated with the display device is substantially reduced by assigning a control code to data which is to be repetitively displayed, for example, spaces at the end of a line or fields of uniform color. Selected elements are thus displayed a predetermined number of times without the need for a corresponding number of memory locations. Incoming data may be sotred in a buffer memory at a greater rate than can be processed by the present system by means of a control circuit which inhibits the inputting of data for a period of time when there is a risk of overwriting or erasure of previously stored data.

Abstract translation: 用于在例如图文电视系统中的光栅扫描显示设备上显示字母数字和图形信息的系统包括更新以改变显示的存储器。 通过为存储器中的一个或多个区域中的每一个分配基地址并且在本地或远程控制下根据需要改变基地址来提供所显示图像的动态变化。 字母数字和图形数据可以通过与要显示的每行或数据行相关联的标识数据组合在单个显示页面上。 通过将控制代码分配给要重复显示的数据（例如在一行或多个均匀颜色的场的空格）来显着减少与显示设备相关联的存储器的所需容量。 所选择的元件因此显示预定次数，而不需要相应数量的存储器位置。 输入数据可以以比当前系统可以通过控制电路更大的速率被存储在缓冲存储器中，该控制电路在存在重写或擦除先前存储的风险的一段时间内禁止输入数据 数据。

公开(公告)号：US4684938A

公开(公告)日：1987-08-04

申请号：US583072

申请日：1984-02-23

Applicant: Gerard Chauvel

Inventor： Gerard Chauvel

IPC: G09G5/36 ,  G09G5/39 ,  G09G1/16

CPC classification number: G09G5/363

Abstract: A system for visualization on a video screen (6) in a graphical mode in which the visual information to be displayed is defined on the screen by a point by point sweeping, from page memory containing, at a given time, all of the video information to be displayed, and a video display processor (4), connected to a random access memory containing said page memory and to a display control unit (37) adapted to convert the information relative to the image composed from the contents of the memory (5) to screen (6) control signals, characterized in that central processing unit (1) is connected to the video display processor (4) by means of a single bus (12) over which are transmitted, on a time shared basis, the address fields and the data fields (15) and in that it includes in addition a control and interpretation circuit (27) capable, in response to an assignment signal generated by said central processing unit, to interpret the address field as an address field per se or as a control field for the video display processor.

Abstract translation: 一种用于以图形模式在视频屏幕（6）上可视化的系统，其中通过逐点扫描在屏幕上定义要显示的视觉信息，从包含在给定时间的所有视频信息的页面存储器 以及连接到包含所述页面存储器的随机存取存储器的视频显示处理器（4）和适于将信息相对于由存储器（5）的内容构成的图像转换的显示控制单元（37） ）屏幕（6）控制信号，其特征在于，中央处理单元（1）通过单个总线（12）连接到视频显示处理器（4），在该总线（​​12）上以时间共享方式发送地址 字段和数据字段（15），并且其还包括控制和解释电路（27），其能够响应于由所述中央处理单元生成的分配信号将地址字段解释为地址字段本身或 作为控制领域 用于视频显示处理器。

公开(公告)号：US4240138A

公开(公告)日：1980-12-16

申请号：US948284

申请日：1978-10-03

Applicant: Gerard Chauvel

Inventor： Gerard Chauvel

IPC: G06F13/16 ,  G06F13/28 ,  G06F3/00

CPC classification number: G06F13/1673 ,  G06F13/287

Abstract: System for direct access to a memory associated with a microprocessor data processing device comprising a direct access interface for introducing or extracting data in the memory during interruptions of the connection between the processing device and the memory, and a buffer interface operable during a portion of the access time of the processing device to the memory, to supply data addresses contained in the memory originating from the processing device and to enable circulation of corresponding data between the processing device and the memory, and during the remainder of the access time of the processing device, to the end of the access time, to store data transferred from the memory and to prevent transmission of data to the memory. A logic circuit controls inhibition of the buffer interface or of the direct access interface and, during the periods of inhibition of the buffer interface, permits the circulation of data and of addresses between the direct access interface and the memory.

Abstract translation: 用于直接访问与微处理器数据处理设备相关联的存储器的系统，包括用于在处理设备和存储器之间的连接中断期间在存储器中引入或提取数据的直接访问接口，以及可在一部分 提供处理设备到存储器的访问时间，以提供包含在来自处理设备的存储器中的数据地址，并且能够在处理设备和存储器之间以及在处理设备的访问时间的剩余时间期间循环相应的数据 在访问时间结束时，存储从存储器传送的数据并防止数据传送到存储器。 逻辑电路控制对缓冲器接口或直接访问接口的禁止，并且在缓冲器接口的禁止期间允许在直接访问接口和存储器之间的数据和地址的循环。

公开(公告)号：US08185666B2

公开(公告)日：2012-05-22

申请号：US11116522

申请日：2005-04-28

Applicant: Gerard Chauvel

Inventor： Gerard Chauvel

IPC: G06F12/00

CPC classification number: G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

Abstract: A processor executes an instruction that causes a comparison to be performed between contents of a first register and contents of a second register and between the contents of the first register and a predetermined value. The instruction is particularly useful for determining whether an attempted access (either a load or write) to an array improperly targets a location outside the boundary of the array. In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.

Abstract translation: 处理器执行使得在第一寄存器的内容和第二寄存器的内容之间以及第一寄存器的内容与预定值之间执行比较的指令。 该指令对于确定对阵列的尝试访问（加载或写入）是否不正确地定位到阵列边界外的位置特别有用。 在一些实施例中，系统（例如，诸如蜂窝电话的通信设备）包括能够执行如上所述的指令的处理器。

公开(公告)号：US07930689B2

公开(公告)日：2011-04-19

申请号：US11186271

申请日：2005-07-21

Applicant: Gilbert Cabillic ,  Jean-Philippe Lesot ,  Gerard Chauvel

Inventor： Gilbert Cabillic ,  Jean-Philippe Lesot ,  Gerard Chauvel

IPC: G06F9/44 ,  G06F12/06 ,  G06F9/26

CPC classification number: G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

Abstract: Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.

Abstract translation: 提供了用于在Java应用程序中访问间接内存的系统，方法和存储介质。 在一些实施例中，提供存储介质，其包括在设备的间接存储器上执行一个或多个操作的Java应用软件。 软件包括创建表示间接存储器的Java类的实例的指令以及使用存储器元件的元素唯一标识符（“euid”）访问间接存储器的存储器元件的指令。 其他实施例提供了一种用于访问设备的存储器元件的方法，包括创建表示存储器元件的Java类的实例，以及使用存储元件的元素唯一标识符（“euid”）访问存储器元件的存储器元件， 其中所述存储器元件未映射到所述处理器的数据存储器空间。

公开(公告)号：US07840784B2

公开(公告)日：2010-11-23

申请号：US10632084

申请日：2003-07-31

Applicant: Gerard Chauvel ,  Serge Lasserre ,  Dominique D'Inverno

Inventor： Gerard Chauvel ,  Serge Lasserre ,  Dominique D'Inverno

IPC: G06F9/32

CPC classification number: G06F9/30069 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/355 ,  G06F12/0253 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/502

Abstract: A processor may execute a test and skip instruction that includes or otherwise specifies at least two operands that are used in a comparison operation. Based on the results of the comparison, the instruction that follows the test and skip instruction is “skipped.” The test and skip instruction may specify that the operands used in the comparison include (1) the contents of two registers, (2) the contents of one register and the contents of a memory location, or (3) the contents of one register and a stack value. In the second mode (an operand being from memory), a register is specified in the test and skip instruction that contains a value from which a pointer may be calculated. The calculated pointer preferably points to the memory location. If a stack value is used in the execution of the test and skip instruction, the instruction may include a reference to a register that points to the top of the stack. Further, the stack pointer may be adjusted automatically if the stack is used to provide an operand for the instruction. Embodiments may include apparatus and methods.

Abstract translation: 处理器可以执行包括或以其他方式指定在比较操作中使用的至少两个操作数的测试和跳过指令。 根据比较结果，测试和跳过指令之后的指令被“跳过”。测试和跳过指令可以指定比较中使用的操作数包括（1）两个寄存器的内容，（2） 一个寄存器的内容和存储器位置的内容，或（3）一个寄存器的内容和堆栈值。 在第二模式（一个来自存储器的操作数）中，在测试和跳过指令中指定一个寄存器，该指令包含可以计算指针的值。 计算出的指针最好指向存储器位置。 如果在执行测试和跳过指令时使用堆栈值，则该指令可以包括对指向堆栈顶部的寄存器的引用。 此外，如果堆栈用于为指令提供操作数，则可以自动调整堆栈指针。 实施例可以包括装置和方法。

公开(公告)号：US07533250B2

公开(公告)日：2009-05-12

申请号：US11188311

申请日：2005-07-25

Applicant: Gerard Chauvel ,  Jean-Philippe Lesot ,  Gilbert Cabillic

Inventor： Gerard Chauvel ,  Jean-Philippe Lesot ,  Gilbert Cabillic

IPC: G06F9/30 ,  G06F9/40 ,  G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F12/1081 ,  G06F9/30174 ,  G06F9/45504 ,  G06F12/0802 ,  G06F2212/6012

Abstract: A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, where the single instruction requires an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by the group of instructions.

Abstract translation: 一种处理器，包括耦合到第一存储单元并包括数据结构的解码逻辑。 处理器还包括耦合到解码逻辑的第二存储单元。 解码逻辑从第一存储单元获得单个指令，并且如果由数据结构中的第一位指示，则处理一组指令来代替单个指令，其中单个指令需要操作数。 如果由数据结构中的第二位指示，则解码逻辑从第一存储单元获得操作数，修改操作数，并将操作数存储到第二存储单元以供指令组使用。

公开(公告)号：US07395413B2

公开(公告)日：2008-07-01

申请号：US10631585

申请日：2003-07-31

Applicant: Gerard Chauvel

Inventor： Gerard Chauvel

IPC: G06F9/30

CPC classification number: G06F9/30134 ,  G06F9/3001 ,  G06F9/30065 ,  G06F9/30101 ,  G06F9/30174 ,  G06F9/325 ,  G06F9/3836 ,  G06F9/3885 ,  G06F12/0253 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/126 ,  G06F2212/502

Abstract: A processor (e.g., a co-processor) capable of executing instructions sequentially, comprises at least two functional hardware resources. When two instructions that are consecutive in program order and are executed on two separate functional hardware resources, the execution of the two instructions may be parallelized if the two instructions are within a hardware loop. The processor thus, may implement a multiply and accumulate process in an efficient manner by performing the multiply instructions concurrently with the add instructions (which require fewer cycles to complete than the multiply instructions).

Abstract translation: 能够顺序执行指令的处理器（例如，协处理器）包括至少两个功能硬件资源。 当以程序顺序连续并且在两个单独的功能硬件资源上执行的两个指令时，如果两个指令在硬件循环内，则两个指令的执行可以并行化。 因此，处理器可以通过与加法指令同时执行乘法指令（与乘法指令相比需要更少的周期来完成）来实现有效方式的乘法和累加过程。

公开(公告)号：US07146613B2

公开(公告)日：2006-12-05

申请号：US10157530

申请日：2002-05-29

Applicant: Gerard Chauvel ,  Dominique D'Inverno

Inventor： Gerard Chauvel ,  Dominique D'Inverno

IPC: G06F9/455 ,  G06F9/45 ,  G06F12/00

CPC classification number: G06F9/45504 ,  G06F8/4434

Abstract: A digital system and method of operation is which the digital system has a processor with a virtual machine environment for interpretively executing instructions. First, a sequence of instructions is received (404) for execution by the virtual machine. The sequence of instructions is examined (408–414) to determine if a certain type of iterative sequence is present. If the certain type of iterative sequence is present, the iterative sequence is replaced (412) with a proprietary code sequence. After the modifications are complete, the modified sequence is executed in a manner that a portion of the sequence of instructions is executed in an interpretive manner (418); and the proprietary code sequences are executed directly by acceleration circuitry (420).

公开(公告)号：US07120715B2

公开(公告)日：2006-10-10

申请号：US09932866

申请日：2001-08-17

Applicant: Gerard Chauvel ,  Dominique D'Inverno

Inventor： Gerard Chauvel ,  Dominique D'Inverno

IPC: G06F13/14

CPC classification number: G06F12/1027 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/30043 ,  G06F9/5094 ,  G06F9/52 ,  G06F12/0292 ,  G06F12/0879 ,  G06F12/0891 ,  G06F12/1081 ,  G06F2201/81 ,  G06F2201/885 ,  G06F2209/5014 ,  G06F2209/5021 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/22 ,  Y02D10/24

Abstract: A digital system and method of operation is provided in which several processors (740(0)–740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priority value by software executing on the processor. A memory management unit (MMU) (700) is connected to receive a request address (742) from each respective processor. The MMU has a set of entries that correspond to pages of address space. Each entry provides a set of attributes for the associated page of address space, including an address space priority value 309a. For each request, the MMU accesses an entry corresponding to the request address and provides an address space priority value associated with that requested address space page. Arbitration circuitry (1430) is connected to receive a request signal from each processor along with the access priority value from each access priority register and the address space priority value from each MMU. The arbitration circuitry is operable to schedule access to the shared resource according to higher of the pair of priority values provided by each processor.

Abstract translation: 提供了数字系统和操作方法，其中若干处理器（740（0）-704（n））连接到共享资源（750）。 每个处理器具有通过在处理器上执行的软件加载访问优先级值的访问优先级寄存器（1410）。 存储器管理单元（MMU）（700）被连接以从每个相应的处理器接收请求地址（742）。 MMU具有一组对应于地址空间页面的条目。 每个条目为相关联的地址空间页面提供一组属性，包括地址空间优先级值309a。 对于每个请求，MMU访问与请求地址相对应的条目，并提供与该请求的地址空间页相关联的地址空间优先级值。 连接仲裁电路（1430），从每个处理器接收来自每个访问优先级寄存器的访问优先级值和来自每个MMU的地址空间优先级值的请求信号。 仲裁电路可操作以根据由每个处理器提供的优先级对中的较高者调度对共享资源的访问。