公开(公告)号：US20230262996A1

公开(公告)日：2023-08-17

申请号：US18169761

申请日：2023-02-15

Applicant: IMEC VZW

Inventor： Maarten Rosmeulen ,  Jiwon Lee ,  Gouri Sankar Kar ,  Swaraj Bandhu Mahato

IPC: H10B99/00

CPC classification number: H10B99/22

Abstract: A charge-coupled device (CCD) memory is provided. In one aspect, the CCD memory is 3D integrated. The CCD memory can include a gate stack with a plurality of gate layers and spacer layers alternatingly arranged one on the other, and a plurality of semiconductor-based channels extending in the stack. The channels may be formed from a semiconductor oxide material. The CCD memory can include dielectric layers, wherein each dielectric layer is arranged between one of the channels and at least one of the gate layers. Each channel of the CCD memory can form, in combination with the gate layers and at least one of the dielectric layers, a string of charge storage capacitors, and each string of charge storage capacitors can be operable as a CCD register. The CCD memory can also include a readout layer, which can include a plurality of readout stages configured to individually readout stored charge from each of the CCD registers.

公开(公告)号：US20220209022A1

公开(公告)日：2022-06-30

申请号：US17646072

申请日：2021-12-27

Applicant: IMEC vzw

Inventor： Nouredine Rassoul ,  Gabriele Luca Donadio ,  Gouri Sankar Kar

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/477

Abstract: The disclosed technology generally relates to a method of processing a field effect transistor (FET) device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or a thin-film-transistor (TFT). In one aspect, the method includes providing a substrate; forming a first oxide semiconductor layer and a second oxide semiconductor layer above the substrate; forming a source structure and a drain structure on the second oxide semiconductor layer; and forming a gate structure on the first oxide semiconductor layer. The first oxide semiconductor layer forms a channel between the source structure and the drain structure. The second oxide semiconductor layer forms a contact layer to the source structure and the drain structure.

公开(公告)号：US11227645B2

公开(公告)日：2022-01-18

申请号：US16705937

申请日：2019-12-06

Applicant: IMEC VZW ,  VRIJE UNIVERSITEIT BRUSSEL

Inventor： Sushil Sakhare ,  Manu Komalan Perumkunnil ,  Johan Swerts ,  Gouri Sankar Kar ,  Trong Huynh Bao

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.

公开(公告)号：US10749106B2

公开(公告)日：2020-08-18

申请号：US15801213

申请日：2017-11-01

Applicant: IMEC VZW

Inventor： Hanns Christoph Adelmann ,  Gouri Sankar Kar ,  Johan Swerts ,  Sebastien Couet

IPC: H01L29/82 ,  H01L43/12 ,  H01L43/10 ,  G11C11/14 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices comprising a magnetic tunnel junction (MTJ). In an aspect, a method of forming a magnetoresistive random access memory (MRAM) includes forming a layer stack above a substrate, where the layer stack includes a ferromagnetic reference layer, a tunnel barrier layer and a ferromagnetic free layer and a spin-orbit-torque (SOT)-generating layer. The method additionally includes, subsequent to forming the layer stack, patterning the layer stack to form a MTJ pillar.

公开(公告)号：US20200185016A1

公开(公告)日：2020-06-11

申请号：US16705937

申请日：2019-12-06

Applicant: IMEC VZW ,  VRIJE UNIVERSITEIT BRUSSEL

Inventor： Sushil Sakhare ,  Manu Komalan Perumkunnil ,  Johan Swerts ,  Gouri Sankar Kar ,  Trong Huynh Bao

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.

公开(公告)号：US10170692B2

公开(公告)日：2019-01-01

申请号：US15387127

申请日：2016-12-21

Applicant: IMEC VZW

Inventor： Gouri Sankar Kar ,  Jürgen Bömmels ,  Davide Crotti

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to semiconductor devices having an integrated magnetic tunnel junction (MTJ), and relates to methods of fabricating the semiconductor devices. In one aspect, a semiconductor device includes a stack including successive layers of: a first metallization layer, a first dielectric layer, a second metallization layer, a second dielectric layer, and a third metallization layer. A magnetic tunnel junction (MTJ) device is formed in the first dielectric layer and in the second metallization layer and electrically connected to a first metallization layer and the third metallization layer.