公开(公告)号：US20220197361A1

公开(公告)日：2022-06-23

申请号：US17563605

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Nir Rosenzweig ,  Krishnakanth V. Sistla ,  Ashish V. Choubal ,  Ankush Varma

IPC: G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/26

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

公开(公告)号：US11366506B2

公开(公告)日：2022-06-21

申请号：US16691873

申请日：2019-11-22

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/32 ,  G06F1/3234

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US20220129031A1

公开(公告)日：2022-04-28

申请号：US17520296

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20220100247A1

公开(公告)日：2022-03-31

申请号：US17033753

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Haake ,  Andrew Herdrich ,  Ripan Das

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US11256657B2

公开(公告)日：2022-02-22

申请号：US16364619

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Tejpal Singh ,  Yedidya Hilewitz ,  Ankush Varma ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Jeffrey Chamberlain

IPC: G06F15/00 ,  G06F15/76 ,  G06F15/78 ,  G06F9/54 ,  G06F9/30 ,  G06F1/3296 ,  G06F1/3234

Abstract: In one embodiment, an apparatus includes an interconnect to couple a plurality of processing circuits. The interconnect may include a pipe stage circuit coupled between a first processing circuit and a second processing circuit. This pipe stage circuit may include: a pipe stage component having a first input to receive a signal via the interconnect and a first output to output the signal; and a selection circuit having a first input to receive the signal from the first output of the pipe stage component and a second input to receive the signal via a bypass path, where the selection circuit is dynamically controllable to output the signal received from the first output of the pipe stage component or the signal received via the bypass path. Other embodiments are described and claimed.

公开(公告)号：US10663998B1

公开(公告)日：2020-05-26

申请号：US16370510

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Tamir Salus ,  Alexander Lyakhov ,  Alexander Gendler ,  Krishnakanth Sistla ,  Ankush Varma ,  Rachid Rayess ,  Nimrod Angel

IPC: H02M3/157 ,  G05F1/613 ,  H02J1/12 ,  H02M3/158 ,  H02M1/00

Abstract: Various embodiments provide a voltage regulator circuit with automatic phase shedding. A control circuit may control first transitions of a power state of the voltage regulator based on an average current draw of the voltage regulator. The control circuit may further control second transitions of the power state of the voltage regulator based on a voltage droop of the output voltage and/or a peak current draw of the voltage regulator. The first transitions may be performed synchronously, and the second transitions may be performed asynchronously. Other embodiments may be described and claimed.

公开(公告)号：US20200089308A1

公开(公告)日：2020-03-19

申请号：US16691873

申请日：2019-11-22

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3234

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US10404152B2

公开(公告)日：2019-09-03

申请号：US15721314

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Srikrishnan Venkataraman ,  Sreedhar Narayanaswamy ,  Jonathan P. Douglas ,  Chih-Chung Jonathan Wei ,  Ankush Varma ,  Narayanan Natarajan

IPC: H02M1/00 ,  G06F1/26 ,  H03L7/099

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.

公开(公告)号：US10310588B2

公开(公告)日：2019-06-04

申请号：US15296096

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Allen W. Chu ,  Ian M. Steiner

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/48

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.

公开(公告)号：US20190103801A1

公开(公告)日：2019-04-04

申请号：US15721314

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Srikrishnan Venkataraman ,  Sreedhar Narayanaswamy ,  Jonathan P. Douglas ,  Chih-Chung Jonathan Wei ,  Ankush Varma ,  Narayanan Natarajan

IPC: H02M1/00 ,  G06F1/26

CPC classification number: H02M1/00 ,  G06F1/26 ,  H02M3/158 ,  H02M3/33561 ,  H02M2001/0009 ,  H02M2001/0012 ,  H02M2001/008 ,  H03L7/099

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.