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公开(公告)号：US10281975B2
公开(公告)日：2019-05-07
申请号：US15190417
申请日：2016-06-23
Applicant: Intel Corporation
Inventor： Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Nir Rosenzweig , Eric Distefano , Ishmael F. Santos , James G. Hermerding, II
IPC: G06F1/00 , G06F1/26 , G06F1/32 , G06F1/3296 , G06F1/3228 , G06F9/30
Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
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公开(公告)号：US10248181B2
公开(公告)日：2019-04-02
申请号：US15381241
申请日：2016-12-16
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Ryan Wells
IPC: G06F1/32 , G06F1/324 , G06F1/3293 , G06F1/3203 , G11C7/22 , G06F13/42 , G06F1/3296 , G06F13/40
Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
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公开(公告)号：US10222851B2
公开(公告)日：2019-03-05
申请号：US15331051
申请日：2016-10-21
Applicant: Intel Corporation
Inventor： Efraim Rotem , Nir Rosenzweig , Doron Rajwan , Nadav Shulman , Gal Leibovich , Tomer Ziv , Amit Gabai , Jorge P. Rodriguez , Jeffrey A. Carlson
Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
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公开(公告)号：US20180260153A1
公开(公告)日：2018-09-13
申请号：US15786424
申请日：2017-10-17
Applicant: Intel Corporation
Inventor： Inder M. Sodhi , Alon Naveh , Doron Rajwan , Ryan D. Wells , Eric C. Samson
CPC classification number: G06F3/0625 , G06F1/3206 , G06F1/3278 , G06F1/3287 , G06F3/0634 , G06F3/0673 , Y02D10/157 , Y02D10/171
Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
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公开(公告)号：US10037067B2
公开(公告)日：2018-07-31
申请号：US15138505
申请日：2016-04-26
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Ryan Wells
CPC classification number: G06F1/324 , G06F1/3203 , G06F1/3293 , G06F1/3296 , G06F13/4068 , G06F13/4282 , G11C7/22 , Y02D10/122 , Y02D10/126 , Y02D10/151
Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US20180059748A1
公开(公告)日：2018-03-01
申请号：US15702970
申请日：2017-09-13
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Doron Rajwan , Dorit Shapira , Nadav Shulman , Tomer Ziv
CPC classification number: G06F1/206 , G01K1/026 , G01K13/00 , G06F1/3206 , G06F1/3234 , G06F1/324 , G06F9/5094
Abstract: In an embodiment, a processor includes a plurality of cores and a plurality of temperature sensors, where each core is proximate to at least one temperature sensor. The processor also includes a power control unit (PCU) including temperature logic to receive temperature data that includes a corresponding temperature value from each of the temperature sensors. Responsive to an indication that a highest temperature value of the temperature data exceeds a threshold, the temperature logic is to adjust a plurality of domain frequencies according to a determined policy that is based on instruction execution characteristics of at least two of the plurality of cores. Each domain frequency is associated with a corresponding domain that includes at least one of the plurality of cores and each domain frequency is independently adjustable. Other embodiments are described and claimed.
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公开(公告)号：US09760158B2
公开(公告)日：2017-09-12
申请号：US14298171
申请日：2014-06-06
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/0757 , Y02D10/126 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
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公开(公告)号：US09535812B2
公开(公告)日：2017-01-03
申请号：US13930212
申请日：2013-06-28
Applicant: Intel Corporation
Inventor： Doron Rajwan , Nadav Shulman , Dorit Shapira , Kosta Luria , Efraim Rotem
CPC classification number: G06F11/3037 , G06F11/3419 , G06F11/3476 , G06F2201/88
Abstract: In an embodiment, a processor includes measurement logic to measure a usage associated with the processor. The processor also includes statistical logic to determine, based on a statistical procedure, whether to provide a permission to record an increase in usage responsive to an indication that the usage has increased by a defined amount. The processor also includes control logic to record the defined increase in usage in non-volatile memory responsive to receipt of the permission to record from the statistical logic. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括用于测量与处理器相关联的使用的测量逻辑。 处理器还包括用于基于统计过程来确定是否提供响应于使用已经增加了定义量的指示来记录使用增加的许可的统计逻辑。 处理器还包括控制逻辑，用于响应于从统计逻辑接收到记录的许可而记录在非易失性存储器中的定义的使用增加。 描述和要求保护其他实施例。
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公开(公告)号：US09268378B2
公开(公告)日：2016-02-23
申请号：US13931128
申请日：2013-06-28
Applicant: Intel Corporation
Inventor： Efraim Rotem , Alon Naveh , Doron Rajwan , Nadav Shulman , Eliezer Weissmann
CPC classification number: G06F1/206 , G06F1/203 , G06F1/3206 , G06F1/3215 , G06F1/3243 , G06F1/3287 , Y02D10/16 , Y02D10/171 , Y02D50/20
Abstract: In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a controller comprising logic at least a portion of which is in hardware. The logic may receive from the temperature sensor the multiplicity of junction temperature measurements and may instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and may instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold. Other embodiments are disclosed and claimed.
Abstract translation: 在一个实施例中，一种装置包括温度传感器，用于对平台中的部件执行多个结温测量，控制器包括至少其一部分处于硬件中的逻辑。 逻辑可以从温度传感器接收多个结温度测量值，并且当结温度测量超过第一阈值时可以指示组件执行部件的第一次掉电动作，并且可以指示组件执行第二次掉电 当基于结温度测量的多重性的平均结温超过第二阈值时，组分的作用。 公开和要求保护其他实施例。
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30.发明授权公开(公告)号：US09176565B2
公开(公告)日：2015-11-03
申请号：US13782578
申请日：2013-03-01
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Weissmann , Ryan Wells
CPC classification number: G06F1/324 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F1/3234 , G06F1/3243 , G06F13/14 , Y02D10/126
Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于确定多域处理器的非核心域不以非核域所请求的频率操作的方法，将来自非核心域的请求发送到功率 控制器降低多域处理器核心域的频率，并响应请求，降低核心域频率。 描述和要求保护其他实施例。
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