公开(公告)号：US20240387396A1

公开(公告)日：2024-11-21

申请号：US18319164

申请日：2023-05-17

Applicant: Intel Corporation

Inventor： Jung Kyu Han ,  Gang Duan ,  Srinivas Pietambaram

IPC: H01L23/544 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: Surface finishes for contacts and fiducial marks on integrated circuit package substrates and associated methods are disclosed. An example integrated circuit (IC) package substrate includes a first solder resist layer; a second solder resist layer opposite the first solder resist layer; and a fiducial marker including tin in an opening in the first solder resist layer.

公开(公告)号：US12125793B2

公开(公告)日：2024-10-22

申请号：US18374576

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Rahul Manepalli ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06582 ,  H01L2225/06589

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20240332100A1

公开(公告)日：2024-10-03

申请号：US18193172

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Pratyush Mishra ,  Marcel Wall ,  Sashi Kandanur ,  Pooya Tadayon ,  Srinivas Pietambaram ,  Benjamin Duong ,  Suddhasattwa Nad

IPC: H01L23/15 ,  H01F27/24 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L23/15 ,  H01F27/24 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5226

Abstract: Glass-integrated inductors in integrated circuit (IC) packages are disclosed. A disclosed IC package includes a glass layer having an aperture extending therethrough, and an inductor in the aperture, the inductor including a metal core extending through the aperture, the metal core electrically coupled to interconnects on opposite sides of the glass layer, and at least one of a ferrite or a magnetic alloy in the aperture and laterally surrounding the metal core.

公开(公告)号：US20240312924A1

公开(公告)日：2024-09-19

申请号：US18122250

申请日：2023-03-16

Applicant: Intel Corporation

Inventor： Shishir Deshpande ,  Jung Kyu Han ,  Gang Duan ,  Srinivas Pietambaram

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/54426 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Microelectronic devices, systems, and techniques are disclosed having package substrate land side fiducial structures that are readily distinguishable from adjacent interconnect structures during registration of the land side of the package substrate. The fiducial structure includes a ring shape, a double ring shape, a donut shape, a triangular shape, an H-shape, or an I-shape in contrast to the circular, square, or rectangular shape of the adjacent interconnect structure. The fiducial structure shape may also have a different size relative to the interconnect structure shape.

公开(公告)号：US20240312865A1

公开(公告)日：2024-09-19

申请号：US18182879

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/3733 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49877 ,  H01L23/15

Abstract: Methods, systems, apparatus, and articles of manufacture to improve reliability of vias in a glass substrate of an integrated circuit package are disclosed. An example integrated circuit (IC) package substrate includes a glass substrate, a via extending between first and second surfaces of the glass substrate, and a conductive material provided in the via, the conductive material including gallium and silver.

公开(公告)号：US12087695B2

公开(公告)日：2024-09-10

申请号：US18224794

申请日：2023-07-21

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Rahul Manepalli ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06582 ,  H01L2225/06589

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US20240222320A1

公开(公告)日：2024-07-04

申请号：US18091265

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/08 ,  H01L25/50 ,  H01L2224/08145

Abstract: Multi-chip/die device including two or more substantially coplanar base IC dies directly bonded to a bridge IC die over or under the base IC dies. Direct bonding of the bridge IC die provides high pitch interconnect. A package metallization routing structure including conductive vias adjacent to the bridge IC die may be built up and terminate at first level interconnect interfaces. A temporary carrier, such as glass, may be employed to form such multi-chip devices.

公开(公告)号：US20240213198A1

公开(公告)日：2024-06-27

申请号：US18087517

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Liang He ,  Yue Deng ,  Gang Duan ,  Jung Kyu Han ,  Ali Lehaf ,  Srinivas Pietambaram

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/13 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13541 ,  H01L2224/1358 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13684 ,  H01L2224/16013 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841

Abstract: An electronic package comprises a first die having at least one first interconnect with solder over or under a first metal feature. A second die has at least one second interconnect to the first die, each second interconnect comprising a second metal feature comprising copper, solder over or under the second metal feature, and a layer between the solder and the second metal feature, wherein the layer comprises iron and has a different material than material of the first interconnect.

公开(公告)号：US11978685B2

公开(公告)日：2024-05-07

申请号：US16522494

申请日：2019-07-25

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Robert L. Sankman ,  Rahul Manepalli ,  Gang Duan ,  Debendra Mallik

IPC: H01L23/15 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/15 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49827 ,  H01L23/5381

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.

公开(公告)号：US20240113005A1

公开(公告)日：2024-04-04

申请号：US17957751

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Hiroki Tanaka ,  Brandon Marin ,  Srinivas Pietambaram ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13

CPC classification number: H01L23/49833 ,  H01L21/4803 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/16 ,  H01L2224/0346 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16146 ,  H01L2224/1624 ,  H01L2224/80201 ,  H01L2224/80379 ,  H01L2924/0665

Abstract: Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.